predict how actual Xbox Next will differ from leaked specs

[Mariner]

I've heard rumours that (eventually) NTL is going to release their own Sky+alike service.

I hope they have TiVo or someone similarly competent writing the software.

I don't hold high hopes for this at the moment, though seeing as how the STB software is pretty bloody awful at the moment. I have to physically unplug mine once a week or so to reset it when the 'programme guide' crashes.

Sounds like you have the same STB as I do!

Don't get me started on that poxy Pace STB.. GRRrrrr.

Actually, I just had a quick look on www.cableforum.co.uk and the indications there are that NTL may be beginning the VOD rollout soon in some areas. God help us all!

 

[pahcman]

I use media streaming with modded Xbox and PC. Works great!

As Dave said, having PC centric is not bad as some make it, the system provides low level functions and high level tweaking. The last thing i want is a dumbed down system with locked "propertiery" functions.

We avid netizens, shouldnt have any problems troubleshooting, not that my current systems have much troubles to shoot. We shouldnt be allow only basic functions to play.

Both CE and PC have their good bad points. Things can only get better. Real blind love to viciously put all bets on one side and thrash the other...

 

[Vince]

I will revisit this argument in a few months. Continuing it now isn't going anywhere at the present time. Although, Gubbi, I never mentioned IP at all.

Argh, do you post utter shit just to disagree? It's not "arguably" at 110nm except in your mind and those similarly biased. Please, show me the 110nm part out there fabricated with gate lengths of 45nm.

You do understand that only chipworks has mysteriously managed to get 45nm and everyone else who's done a cross section has gotten much larger critical dimensions, don't ya? And that marvelous chipworks report only came out after sony had egg on its face over its claims. Hmm...

Ok, this is just insane. Who are these mysterious people who compose "everyone else"? What I find most funny, outside of the fact that you keep post utter shit and then preach to some supposed authority as a basis for these comments, is that it was - in fact - SI (the source of the false charges) that recanted and actually issued a press release on the EE+GS commending it on it's SoC innovation, admitting to the 65nm gate lengths, and stating the design is a "very judicious trade-off between performance and manufacturability."

So, now I get to ask you. Who the f- are you to state that Chipworks is lying? Why should we cover ourselves in tin-foil and believe you in that Sony, Toshiba, Chipworks and SI are all wrong because of a single early and incorrect report that caused alot of commotion and was later backed-away from? Please, lay it all out... explain to me why the 45nm gates that I can see with my own eyes don't exist and weren't fabricated with 193 nm lithography.

I'm pretty sure that either TI or Intel would gladly put the performance of their fets up against Sony's. I'm not at all convinced that you even have a clue about semiconductors.

Yeah, cute. Pass me the tin-foil and lets talk about more conspiracies, ok?

 

[Qroach]

vince, do you need to act like an asshole when you reply to posts? is it necessary?

 

[AzBat]

vince, do you need to act like an asshole when you reply to posts? is it necessary?

I'm wondering the same thing.

Tommy McClain

 

[Dave Baumann]

Who are these mysterious people who compose "everyone else"?

Its fairly common practice for one company to analyse another ASIC's in fairly high detail, although they don't speak of it. I've recieved enourmously detailed reports on graphics ASIC's in the past. I would put the "everyone else" as "any other semiconductor company that has a vested interest in high performance processes".

 

[nelg]

explain to me why the 45nm gates that I can see with my own eyes

F_uk you have good eyesight.

 

[Vince]

Its fairly common practice for one company to analyse another ASIC's in fairly high detail, although they don't speak of it. I've recieved enourmously detailed reports on graphics ASIC's in the past. I would put the "everyone else" as "any other semiconductor company that has a vested interest in high performance processes".

I know, point me towards one. There are several publicaly traded companies that do exactly this, I want to see them. Because Chipworks and SI both state that there are 45nm gates in the design, not to mention the physical die sizes that exist as support.

And I don't have to be an asshole unless someone posts something so ridiculous that it's irritating. If his username was 'Deadmeat' and he posted the same rant about how it's not a 90nm design and that Chipworks report was some cover-up after Sony got " egg on its face", he would have been bashed right and left. But, he wasn't because of some false appeal to authority that doesn't exist.

EDIT: How about this, can I go in the 3D forum and post that ATI is lying because their 9600XT has gate lengths of 85nm and really isn't a 130nm device as claimed? Lets see how long that thread goes before the comments that make mine look tame start.

 

[one]

in fact - SI (the source of the false charges) that recanted and actually issued a press release on the EE+GS commending it on it's SoC innovation, admitting to the 65nm gate lengths, and stating the design is a "very judicious trade-off between performance and manufacturability."

Since I didn't know it, I searched and found the release. Haha, aaronspink, before having egg on your face, please use Google as I asked before!

http://www.semiconductor.com/resources/press_releases/2004_02_18_1.asp?c=71744

Press Release Hot PartsView Our Hot Parts New ReportsView Our Latest Reports
Semiconductor Insights Recognizes Sony for SoC Innovations

FOR IMMEDIATE RELEASE:

SAN FRANCISCO, California February 18, 2004 — Semiconductor Insights (SI), the leader in technology and patent analyses of integrated circuits and structures, today announced the latest results of its continuing investigation of the Sony PlayStation PSX, including the Emotion Engine + Graphics Synthesizer (EE+GS) chip. "Our initial announcement regarding Sony's EE+GS chip generated a lot of interest in this device", said Dr. Doug Smeaton, President and CEO of Semiconductor Insights. "However, much of the early attention was focused on gate length. Overlooked in the discussion was the significant achievement of integrating the sophisticated logic of their Emotion Engine and the embedded memory and graphics processing functions of their Graphic Synthesizer onto a single chip."

SI's preliminary analysis included a minimum physical gate length measurement of 65nm, which has since been confirmed as correct by sources at Sony.

SI's subsequent analyses reveal a very judicious trade-off between performance and manufacturability. The design required only five levels of copper metallization, although the process is reportedly capable of eleven. Low-k, carbon doped dielectric is used, but only as needed, with fluorinated glass and undoped oxide used elsewhere to ensure reliability. The 32M of embedded DRAM are augmented by an additional 2M for redundancy, ensuring a high yield design. Considerable effort appears to have been expended in shrinking the Graphics Synthesizer portion of the design, resulting in an approximately 50% area reduction over the previous generation. "This is a solid design, striking a good balance between cost and performance", said Dr. Smeaton.

"We are pleased that SI's ongoing high level of investment in proprietary tools and sophisticated laboratory resources enables us to accurately analyze even the most advanced chips", said Dr. Smeaton. "With positive confirmation of our initial results by Sony, we are continuing our investigation."

For additional details on the Sony PlayStation PSX, Intel Prescott, other 90nm devices, strained silicon, low-k, and/or related analysis available from Semiconductor Insights, please visit www.semiconductor.com.

 

[AzBat]

And I don't have to be an asshole unless someone posts something so ridiculous that it's irritating. If his username was 'Deadmeat' and he posted the same rant about how it's not a 90nm design and that Chipworks report was some cover-up after Sony got " egg on its face", he would have been bashed right and left. But, he wasn't because of some false appeal to authority that doesn't exist.

You don't have to post that way period. No matter who you're replying to or if they're irrating. BTW, you even post that way to Dave, the guy that owns and runs this site. It's called manners and decency. Something others have learned and you have yet to grasp. If you talk like this with people in a public forum, then I wonder how you talk to people in person. I bet mom is real proud.

Tommy McClain

 

[Dave Baumann]

Since I didn't know it, I searched and found the release. Haha, aaronspink, before having egg on your face, please use Google as I asked before!

Clearly I'm missing something here - Vince claims gate lengths of 45nm, the "retraction" from SI doesn't appear to be a retraction of their initial comments but an but an acknowledgement that they "have made significant advancements", but in that same statement they also say "SI's preliminary analysis included a minimum physical gate length measurement of 65nm, which has since been confirmed as correct by sources at Sony." which is, as far as I can see, what they initially stated.

What's missing here?

 

[one]

Since I didn't know it, I searched and found the release. Haha, aaronspink, before having egg on your face, please use Google as I asked before!

Clearly I'm missing something here - Vince claims gate lengths of 45nm, the "retraction" from SI doesn't appear to be a retraction of their initial comments but an but an acknowledgement that they "have made significant advancements", but in that same statement they also say "SI's preliminary analysis included a minimum physical gate length measurement of 65nm, which has since been confirmed as correct by sources at Sony." which is, as far as I can see, what they initially stated.

What's missing here?

http://www.semiconductor.com/resources/newsletters/82_eegs90nm.asp

While Sony's EmotionEngine+Graphics Synthesizer (EE+GS) found in the latest PlayStation PSX is an impressive device, it remains closer to the 130nm than the 90nm process node as defined by the ITRS roadmap. This has sparked renewed industry interest in what constitutes 90nm.

Here is Semiconductor Insights' most recent SEM cross-section of the EE+GS with an average gate length (LG) of 65nm.

This measurement has been confirmed by sources at Sony and reinforced by Sony's own documentation and a joint paper between Toshiba and Sony presented at IEDM. According to the ITRS roadmap, a nominal LG of 37nm would qualify as 90nm. The smallest gates on the IBM PowerPC 750FX — a 130 nm design — were 55 nm. However, LG can be a very confusing indicator of technology, since gate lengths have scaled more aggressively than the stated minimum feature size for a given lithography node ever since the 0.25 � generation.

Semiconductor Insights is publishing a report that will define the 90nm process node providing a baseline against which to accurately measure Sony's progress towards 90nm with the EE+GS. Detailed technical analyses of the EE+GS will be included in this report.

 

[aaaaa00]

According to the ITRS roadmap, a nominal LG of 37nm would qualify as 90nm. The smallest gates on the IBM PowerPC 750FX — a 130 nm design — were 55 nm. However, LG can be a very confusing indicator of technology, since gate lengths have scaled more aggressively than the stated minimum feature size for a given lithography node ever since the 0.25 � generation.

65 nm > 55 nm > 37 nm.

LG has to be ~37 nm to qualify as a 90 nm process "according to the ITRS roadmap".

Or am I reading this wrong?

 

[Dave Baumann]

Here is Semiconductor Insights' most recent SEM cross-section of the EE+GS with an average gate length (LG) of 65nm

The "average" appears to refer to the average of measurements taken from a single transistor. The report also does not appear to be backing down from their initial statement at all and they are sticking to their initial point that the gate length is 65nm, not 45nm as Vince and Chipworks puts forth. If you click on the "Sony's own documentation" link that you quoted from from the second SI report you would see that it goes to a PDF on sony.net talking about the EE+GS that quite clearly states the gate lengths are 70nm - not 45nm.

 

[one]

According to the ITRS roadmap, a nominal LG of 37nm would qualify as 90nm. The smallest gates on the IBM PowerPC 750FX — a 130 nm design — were 55 nm. However, LG can be a very confusing indicator of technology, since gate lengths have scaled more aggressively than the stated minimum feature size for a given lithography node ever since the 0.25 � generation.

65 nm > 55 nm > 37 nm.

LG has to be ~37 nm to qualify as a 90 nm process "according to the ITRS roadmap".

Or am I reading this wrong?

Well that's a long story but to cut it short according to Intel it's well in the range of the 90nm process.

 

[Dave Baumann]

Well that's a long story but to cut it short according Intel it's well in the range of the 90nm process.

And this goes back to Aaron's initial comment.

 

[one]

Here is Semiconductor Insights' most recent SEM cross-section of the EE+GS with an average gate length (LG) of 65nm

The "average" appears to refer to the average of measurements taken from a single transistor. The report also does not appear to be backing down from their initial statement at all and they are sticking to their initial point that the gate length is 65nm, not 45nm as Vince and Chipworks puts forth. If you click on the "Sony's own documentation" link that you quoted from from the second SI report you would see that it goes to a PDF on sony.net talking about the EE+GS that quite clearly states the gate lengths are 70nm - not 45nm.

Yeah Chipworks found 45-50nm gate transistors, like an Intel 90nm chip has a gate length of 45nm. What's wrong with that?

 

[aaaaa00]

Well that's a long story but to cut it short according Intel it's well in the range of the 90nm process.

Hm. According to the PDF at http://www.semiconductor.com/mysi/index.asp?destination=134

the measured LG on the prescott is ~50 nm....

65 nm (EE+GS) > 50 nm (Prescott) > 37 nm (ITRS)...

So neither qualifies as 90 nm "according to the ITRS roadmap", though Prescott is closer...

but then Chipworks says EE+GS has LG of 45nm...

Whom to believe... whom to believe... :?

 

[Akumajou]

predict how actual Xbox Next will differ from leaked specs

Well, I hope that the specs that change have at least an ATI R6X0 GPU in a single or dual GPU set up and 1024MB GDDR3/4 as a bare minimum along along with a cartridge port to give devs the option of making cart games if they feel like it and probably games that use the cart+DVD or HD media combined.

As for the CPU, just a dual dual-core with everything either at .065nm process or smaller if possible and a Nov 2006 release date.

 

[Dave Baumann]

Yeah Chipworks found 45-50nm gate transistors, like an Intel 90nm chip has a gate length of 45nm. What's wrong with that?

Eh? You started off by telling everyone Aaron had egg on his face because be SI "refuted" their initial statement, which I have still not seen to be the case - SI appear to consistently state 65nm average (pre and post "refutement"). You are now using the Chipworks material which Aaron had already acknowledged.

But, the question remains, why does Sony's own documentation state 70nm gate lengths for their 90nm process?