predict how actual Xbox Next will differ from leaked specs

[one]

65 nm > 55 nm > 37 nm.

65nm is the average gate length in an EE+GS and 55nm is the smallest gate length in a PPC750FX.

 

[one]

Yeah Chipworks found 45-50nm gate transistors, like an Intel 90nm chip has a gate length of 45nm. What's wrong with that?

Eh? You started off by telling everyone Aaron had egg on his face because be SI "refuted" their initial statement, which I have still not seen to be the case - SI appear to consistently state 65nm average (pre and post "refutement"). You are now using the Chipworks material which Aaron had already acknowledged.

But, the question remains, why does Sony's own documentation state 70nm gate lengths for their 90nm process?

Ask SI about that. Here's their first PR which is too vague to see how they determined as such.

 

[aaaaa00]

65 nm > 55 nm > 37 nm.

65nm is the average gate length in an EE+GS and 55nm is the smallest gate length in a PPC750FX.

Uh, I read that as the average gate length of A GATE, not the average of all gates in the chip. Or maybe I'm reading it wrong.

In the photo:

(67+63+67)/3 = 65.6 nm

 

[Dave Baumann]

Thats how I was reading it as well.

 

[one]

To answer

Eh? You started off by telling everyone Aaron had egg on his face because be SI "refuted" their initial statement, which I have still not seen to be the case - SI appear to consistently state 65nm average (pre and post "refutement").

specifically this part I'd like to quote from this news letter from SI itself again :

However, LG can be a very confusing indicator of technology, since gate lengths have scaled more aggressively than the stated minimum feature size for a given lithography node ever since the 0.25 � generation.

and the number on ITRS roadmap is only one of possible indicators of the process rule actually used in manufacturing chips.

 

[Dave Baumann]

Ask SI about that. Here's their first PR which is too vague to see how they determined as such.

That PR references their initial report (not available publically) to which the synopsis of the report is "The brain of the PSX is the SoC implementation of the combined Sony Emotion Engine and Graphics Synthesizer. Sony's roadmap indicated this devices would be manufactured in a 90 nm process, but it is in fact 130 nm.". The "retration" also states "SI's preliminary analysis included a minimum physical gate length measurement of 65nm, which has since been confirmed as correct by sources at Sony." - clearly they are sticking by their initial statement with regards to gate lenghts.

Note, as well, that this second release where they claim it has been backed up by Sony sources is some 14 days after the Chipworks release.

 

[one]

Uh, I read that as the average gate length of A GATE, not the average of all gates in the chip. Or maybe I'm reading it wrong.

Read more detailed reports from SI at eetimes.

"We took a cross-section through a dense logic area and measured the smallest gate lengths we could find and compared them with the ITRS road map," said Edward Keyes, chief technology officer of Semiconductor Insights, referring to the International Technology Roadmap for Semiconductors. "That says an LG [gate length] of 37 nm equates to a 90-nm process. We found the smallest LG was 70 nm, which equates to a 130-nm process. The ITRS specifies an LG of 65 nm for a 130-nm process."

Then Chipworks found a 45nm transistor in the same chip

 

[Dave Baumann]

I still think that "smallest" refers to the "smallest average gate length".

But another question remains if an LG of 37nm equates to 90nm process, what LG is there for 110nm? (along with the other question of "why does Sony describe this as having an LG of 70nm"?)

 

[Dave Baumann]

Unfortunaly we can only see the TOC, but it appears that Chipworks own detailed report, published after their initial release that states 45nm, indicates that they also think the gate sizes for EE+GS are between 65-70nm.

Sample Report - for Customer Review: Sony CXD9797GB EmotionEngine + GraphicsSynthesizer Structural Analysis
Page 5: "3.7.5 65-70 nm Gate Length Transistors"
Rev 1.0 - Mar 22, 2004 01:08

So, whos going to stump up the cash to buy the full report?

 

[one]

You can see the ITRS roadmap 2004 updates and it shows the 90nm technology node based on DRAM half-pitch (hp90) and its MPU gate length after etch is 37nm, but it's more like the 65nm technology node based on processor physical gate length which is used to indicate the technology generation for commercial use.

http://public.itrs.net/Files/2002Update/2002Update-Glossary.pdf

Technology Node—The ground rules of process governed by the smallest feature printed. The half-pitch of first-level interconnect dense lines is most representative of the DRAM technology level required for the smallest economical chip size. For logic, such as microprocessors (MPUs), physical bottom gate length is most representative of the leading-edge technology level required for maximum performance. MPU and ASIC logic interconnect half-pitch processing requirement typically refers to the first polysilicon or metal layer and lags behind DRAM half-pitch, which may also refer either first layer metal or polysilicon. The smallest half-pitch is typically found in the memory cell area of the chip. Each technology node step represents the creation of significant technology progress—approximately 70% of the preceding node, 50% of two preceding nodes. Example: DRAM half pitches of 180, 130, 90, 65, 45, 32 nm, and 22 nm. For cost reasons, high-volume, low-cost ASIC gate-length requirements will typically match DRAM half-pitch targets, but the low-volume leading-edge high-performance ASIC gate-length requirements will track closely with MPUs.

Also see the glossary in the 2004 updates for the technology node (I couldn't copy the text in Acrobat as the pdf is DRM'ed this year so I put 2002 one above!),

An official 2003 ITRS metal half-pitch node indicator, "hpXX", has been added to differentiate the ITRS definition from commercial technology generation numbers.

Intel and others are just buying IC steppers from 3 major makers - Nikon (Japan), Canon (Japan), ASML (Netherlands), so there are no significant time differences between the dates semiconductor companies start to apply a newer process technology.

 

[Riddlewire]

Please forgive my total lack of authority in this matter, but this thread either needs to get back on topic or be closed. This entire last page has nothing to do with the original topic.

 

[AlNom]

IMO, there is no point to the original purpose of the thread...


Edit: It's basically asking about made up stuff from leaked/rumoured stuff and trying to compare it to stuff that's not even out yet.

SO... to me the thread read like this: Predict how different our predictions are from the rumoured/leaked specs. Wow.

 

[Wunderchu]

Please forgive my total lack of authority in this matter, but this thread either needs to get back on topic or be closed. This entire last page has nothing to do with the original topic.

IMO, changing topics within a thread is fine, as long as the new topic(s) are still relevant to the section of the forum that the thread is in....

in other words, since some of the stuff posted on these last few pages is still relevant to Beyond3D 's "Console Talk" forum, it is fine IMO, and does not quite warrant closing of the thread..

 

[Riddlewire]

IMO, changing topics within a thread is fine, as long as the new topic(s) are still relevant to the section of the forum that the thread is in....

In that case, why bother with thread topics at all?
Each day should just start with a new "Console Discussion" thread and it can take shape however organically it needs. As long as console matters are discussed, there's no need for separate threads.
Or here's a better idea: Why not just mandate that all threads, no matter what the original topic, must morph into a PS2/PS3 discussion by no later than page 5. That would then be in accordance with standard B3D Forum practices...

 

[cthellis42]

Unfortunatly TiVo is kinda dead over here - the only manufacturer of units for the UK, Thompson, gave up about a year ago and I'm not aware of any others that have taken up the position. There is, however, quite a modding community - the unit has one PCI port that you can install a wireless network adapter to and you can install the drivers seeing as it is just Linux; I've always been a little temped to do it. However, all of this modding become much easier with MCE and its becoming increasingly attractive.

TiVo may well become outmoded in the future, but for right now it's got a large installed base and "the name." The problem is, they're slower to innovate on the hardware end (which means eventually they're going to get overcome as the manufacturers start rolling our decent PVR capabilities in their own units) but good on the software end--which helps the generalized innovation that way.

Their problem is, I think, that they will become overwhelmed eventually by the content providers bundling in their own personal units with their services for a lower cost (and easier convenience) than TiVo (which is why I'm sure TiVo is looking specifically into licensing the way they do with DirecTV). At the moment they're behind the curve, but once getting a HDPVR/tuner is cheap and easy enough when you get your cable/satellite service to begin with... Well, it'll be much harder for TiVo to validate themselves.

However, their past and current innovations--which is what I was talking about--are likely to be standards. Both for TiVo to compete with other devices (like dedicated PC's, which it currently beats the snot out of price-wise), and then for everyone else to try to compete with TiVo. Any way you piece it together, those features will come. It's one of the easier forms of digital convergence, and I would all next gen's consoles to have it in some way themselves, too.

 

[cthellis42]

Or here's a better idea: Why not just mandate that all threads, no matter what the original topic, must morph into a PS2/PS3 discussion by no later than page 5. That would then be in accordance with standard B3D Forum practices...

Too true, too true...

 

[Vince]

The "average" appears to refer to the average of measurements taken from a single transistor. The report also does not appear to be backing down from their initial statement at all and they are sticking to their initial point that the gate length is 65nm, not 45nm as Vince and Chipworks puts forth. If you click on the "Sony's own documentation" link that you quoted from from the second SI report you would see that it goes to a PDF on sony.net talking about the EE+GS that quite clearly states the gate lengths are 70nm - not 45nm.

Dave, look this isn't that hard. First of all, that "documentation" is on Sony's ASC9, not the OTSS based CMOS4 AFAIK. Secondly, The EE+GS is a closed design which doesn't need to ramp in preformance, Sony having combined the two ICs are aiming to maximize yeild and profitability, not preformance. There is little need to push every logic gate as the design is bounded to 300MHz, it just isn't logical (pardon the pun) from their point of view from a static preformance cap that's already well, well under what the design is capable of.

Now, the CMOS4 process is capable of 45nm gates, this was theoretically proposed here:

<center><img src=http://pc.watch.impress.co.jp/docs/2003/0421/sony1_04.jpg height=170 width=250></center>

Forthermore, the very existence of measurable and observable gate lengths of 45nm demonstrates that the CMOS4 process is 90nm capable according to Intel's guidelines. Do you not comprehend this? The very existence of the following pictures proves beyond any possible rational argument that it's a 90nm process stepping fabricated with fabricated with 193 nm lithography.

<center><img src=http://www.chipworks.com/mail/2004_02/sony_90nm.jpg height=130 width=150> <img src=http://www.chipworks.com/news/newsimages/SonyPSX.gif height=130 width=200>
Sony's CXD9797GB</center>

It works like a production maximization curve Dave, you have an outer bound that's the maximum attanable gate length which yeilds the maximum preformance. You then, as in the production maximization example, can have data points under the curve. In the EE+GS's case wrt CMOS4 (which is the bound), they went to max productivity and yeilds (profits), which adds another dimension to the analysis and pushes the equilibrium point from the edge. How hard is this to grasp?

If CMOS4 isn't 90nm and fabbed with 193nm lithography, then how the hell are there 45nm gates in the design? And if you conceed, as an f-ing rational person would that (as you can clearly see above) even one does exist, then you must conceed that CMOS4 is a 90nm process.

And if you don't then we can turn this on ATI and attack them on their blatent lying concerning saying their design is 130nm yet they have a mean gate length of 86nm (WTF is that?!?), on nVidia and Intel and TI and everyone who doesn't push the process technology in every non-critical sector of their design. Your argument is untenable and, frankly, stupid.

 

[Dave Baumann]

Yep, you really are an asshole Vince.

Look, do you comprehend this - there are currently 3 sources in this thread that have looked at the EE+GS in actuality, not theoretically: two of those sources state gate lengths of ~65nm, SI and, yes, Sony's own documentation that looks specifically at the implementation of the EE+GS - do you comprehend that? The third source, the only one that I have so far seen as identify 45nm gate lengths has documentation available that appears to contradict their own initial findings - so, is it possible that this source may have been initially incorrect, especially since their later findings appear to concur with both Sony's document and the finding that SI have stuck to from the beginning despite pressure to the contrary.

If there are "some" 45nm gate lengths in the EE+GS then a.) Why doesn't Sony's documentation state that, b.) why have SI consistently stuck to the 65nm quote and not acknowledged them, and c.) why is there no reference to them in the Chipworks detailed analysis document, but only referencing 60-70nm gate lengths?

And if you don't then we can turn this on ATI and attack them on their blatent lying concerning saying their design is 130nm yet they have a mean gate length of 86nm (WTF is that?!?), on nVidia and Intel and TI and everyone who doesn't push the process technology in every non-critical sector of their design. Your argument is untenable and, frankly, stupid.

Before you start going around calling peoples arguments stupid perhaps you ought to stop and read for a minute – I’ve not actually touched on whether this is “90nm or notâ€￾, I have merely been trying to establish the gate lengths so far, so its stupid of you to assume that I’ve argued against it being 90nm yet.

 

[Inane_Dork]

Who the flip cares about the nm rating of your gates? GOSH.[/Napoleon]

 

[Vince]

If there are "some" 45nm gate lengths in the EE+GS then a.) Why doesn't Sony's documetation state that, b.) why have SI consistently stuck to the 65nm quote and not acknowledged them, and c.) why is there no reference to them in the Chipworks detailed analysis document, but only referencing 60-70nm gate lengths?

• a) Did you not see the first picture I posted? Try looking this time, and then you can read the CX-News and the Sony/Toshiba docs like the rest of us and see that they've been stating it's a 90nm process.
• b) They did, you're just ignorant. (see below dialogue)
• c) Ask Chipworks, they clearly have stood by the obvious assumption that the 193nm lithography technology supports 90nm (duh) and that there are 45nm gate lengths in the design (duh), leading one to conclude this is a relaxed IC (duh) on a 90nm capable process (CMOS4).
• d) Call me an asshole all you want, you're still wrong.

• Reasons why measurements may differ
  
  Keyes said he was reluctant to comment on the Chipworks scanning electron microscope photograph as he did not know how the microscope had been set-up to take the photograph. "There are a couple of reasons you might get different measurements though."
  
  Keyes said that typically gate polysilicon is etched back in preparing the sample. This produces sharp edges that will emit electrons strongly. This can make the surrounding buffer oxides appear thicker than they really are, and make the gate appear shorter.
  
  The second possibility is the geometrical effect of taking an end-of-gate slice, rather than going through the middle of the transistor, when cross-sectioning the chip.
  
  Rather like slicing though the edge, rather than the middle of an orange this has the effect of making the polysilicon gate (the flesh of the orange) look narrower and the oxides (the pith) appear wider.
  
  When asked how it was possible to know whether a sliced transistor was a good representation of the gate length or an end-of-gate aberration, Keyes said: "It comes down to the law of averages. If 99 percent are the transistors are constant and there's a few 30 percent smaller you discount it."
  
  Keyes acknowledged that he would expect end-of-gate slices to vary and not to show identical reduced measurements.
  
  Keyes added that Semiconductor Insights assessment had not just rested on the lack of sub-70-nm gate length transistors but also on the metal-one pitch which had measured at 260-nm. Keyes said the ITRS definition gives 210-nm for a 90-nm manufacturing process and 295-nm for a 130-nm process.
  
  Chipworks findings
  
  Dick James, senior technology analyst for Chipworks, said that although the two transistors Chipworks had photographed were measured to be below 50-nm in gate length he could not identify where in the EE+GS processor the sub-50-nm transistors had been found. This, he said, was because, until an example chip is delayered, the characteristic transistor layout remains hidden under upper metal layers.
  
  James also said he believed that the transistors Chipworks had found were not end-of-transistor anomalies, because several transistors in a line had produced similar measurements in each transistor. If an end-of-transistor anomaly was being measured you would expect the measurements to vary, he said, unless the cut happened to hit the arc of each transistor-end in exactly the same place.
  
  James also said that Chipworks was familiar with edge-effects in samples prepared for scanning electron microscopy by etching. "There is a bit of distortion depending on beam energy. But when you're looking at a gap like this I've got more confidence. Our SEMs are calibrated to within plus or minus 5 percent," said James.
  
  "We did see wider polysilicon lines. But we see p-channel transistors at 48 to 49-nm and n-channel transistors at 46 to 47-nm. The embedded DRAM is more relaxed but you'd expect that."
  
  After studying Chipworks' photograph Semiconductor Insights' Keyes wrote an email to Silicon Strategies saying: "It's apparent that the line-end effect that we talked about is not occurring in this cross-section and hence cannot be the explanation for their smaller measurement. We do still stand by our original statement that this is not 90-nm technology according to the roadmap and we will be investigating further."

  
  Talk about SI backing off and retreating to the ITRS guidelines... Yeah, they did a hell of a job explaining how, exactly, those 45nm gates got there if the process was only capable of 130nm.
  
  

  Referring to "misunderstandings" in the way Semiconductor Insights measured the EE+GS processor, engineering sources at Sony acknowledged that Sony used a geometry rule "a little bit more relaxed than 90 nm" in certain portions of the EE part of the design. Sony said the GS block was completely redesigned based on a 90-nm library. The embedded-DRAM block is one generation behind the logic, and uses a 130-nm process, according to a second Sony spokesman.

  
  Which just happens to co-inside with what Chipworks found and I've been stating. Bizzare, huh?

Before you start going around calling peoples arguments stupid perhaps you ought to stop and read for a minute – I’ve not actually touched on whether this is “90nm or notâ€￾, I have merely been trying to establish the gate lengths so far, so its stupid of you to assume that I’ve argued against it being 90nm yet.

The argument (aaron's) is stupid. You just jumped to his defense as usual. Explain how you fabricate a single damned 45nm gate with 130nm lithography technology. Please, explain how the following pictures can exist if the process isn't 90nm?

<center><img src=http://www.chipworks.com/mail/2004_02/sony_90nm.jpg height=130 width=150> <img src=http://www.chipworks.com/news/newsimages/SonyPSX.gif height=130 width=200>
Sony's CXD9797GB</center>

Answer: It can't. As I already stated:

<blockquote>It works like a production maximization curve Dave, you have an outer bound that's the maximum attanable gate length which yeilds the maximum preformance. You then, as in the production maximization example, can have data points under the curve. In the EE+GS's case wrt CMOS4 (which is the bound), they went to max productivity and yeilds (profits), which adds another dimension to the analysis and pushes the equilibrium point from the edge. How hard is this to grasp?</blockquote>