DaveBaumann said:
You talk about nothing but the obvious here. But it fails to address the question – why does Sony’s documentation for EE+GS only reference gate lengths of 70nm if there are supposedly 45nm gate lengths in use?
Thats not EE+GS documentation, it's on ASC9. How many times must I repeat. SCE's roadmap, which I posted, clearly states a 45nm gatelength minimum for 90nm node. We have physical evidence of this in the SEMs. 1+1=2 in theory and praxis. This is open and shut.
DaveBaumann said:
Vince said:
No, they just said that they can't explain how those 45nm gates got into the design that they claim is 130nm.
No, they said they can’t explain how SI
measured 45nm gates,
not that they concur there are 45nm gates.
Uh, try comprehending. First of all, it's SI addressing Chipworks 45nm SEMs. Secondly, if you read this and comprehend it it's clear that SI states that they can't explain how the 45nm gates were produced. Their initial responce was that it's an imaging problem, but this was proven incorrect. As stated, they have no responce for how the 45nm gates exist.
<blockquote>
Silicon Insider said:
Reasons why measurements may differ
Keyes said he was reluctant to comment on the Chipworks scanning electron microscope photograph as he did not know how the microscope had been set-up to take the photograph. "There are a couple of reasons you might get different measurements though."
Keyes said that typically gate polysilicon is etched back in preparing the sample. This produces sharp edges that will emit electrons strongly. This can make the surrounding buffer oxides appear thicker than they really are, and make the gate appear shorter.
The second possibility is the geometrical effect of taking an end-of-gate slice, rather than going through the middle of the transistor, when cross-sectioning the chip.
Rather like slicing though the edge, rather than the middle of an orange this has the effect of making the polysilicon gate (the flesh of the orange) look narrower and the oxides (the pith) appear wider.
When asked how it was possible to know whether a sliced transistor was a good representation of the gate length or an end-of-gate aberration, Keyes said: "It comes down to the law of averages. If 99 percent are the transistors are constant and there's a few 30 percent smaller you discount it."
Keyes acknowledged that he would expect end-of-gate slices to vary and not to show identical reduced measurements.
Keyes added that Semiconductor Insights assessment had not just rested on the lack of sub-70-nm gate length transistors but also on the metal-one pitch which had measured at 260-nm. Keyes said the ITRS definition gives 210-nm for a 90-nm manufacturing process and 295-nm for a 130-nm process.
Chipworks findings
Dick James, senior technology analyst for Chipworks, said that although the two transistors Chipworks had photographed were measured to be below 50-nm in gate length he could not identify where in the EE+GS processor the sub-50-nm transistors had been found. This, he said, was because, until an example chip is delayered, the characteristic transistor layout remains hidden under upper metal layers.
James also said he believed that the transistors Chipworks had found were not end-of-transistor anomalies, because several transistors in a line had produced similar measurements in each transistor. If an end-of-transistor anomaly was being measured you would expect the measurements to vary, he said, unless the cut happened to hit the arc of each transistor-end in exactly the same place.
James also said that Chipworks was familiar with edge-effects in samples prepared for scanning electron microscopy by etching. "There is a bit of distortion depending on beam energy. But when you're looking at a gap like this I've got more confidence. Our SEMs are calibrated to within plus or minus 5 percent," said James.
"We did see wider polysilicon lines. But we see p-channel transistors at 48 to 49-nm and n-channel transistors at 46 to 47-nm. The embedded DRAM is more relaxed but you'd expect that."
After studying Chipworks' photograph Semiconductor Insights' Keyes wrote an email to Silicon Strategies saying: "It's apparent that the line-end effect that we talked about is not occurring in this cross-section and hence cannot be the explanation for their smaller measurement. We do still stand by our original statement that this is not 90-nm technology according to the roadmap and we will be investigating further."
</blockquote>
You want to debate semantics, go right ahead. This is clear as day to anyone who doesn't have their head in their ass.
DaveBaumann said:
And they are from their initial statement published in February, their detailed report was published in March – and subsequently appears not to reference any 45nm gate lengths; if those are the case then why aren’t they referenced in the subsequent detailed report?
So what are you saying Dave, that they fabricated and lied when they published this:
<center>
<img src=http://www.chipworks.com/mail/2004_02/sony_90nm.jpg height=130 width=150> <img src=http://www.chipworks.com/news/newsimages/SonyPSX.gif height=130 width=200>
Sony's CXD9797GB</center>
Seriously, give me some rational explination other than this consistent spewing of bs and semantic crap. Either this SEM is real or it's fake, either they lied or they didn't. What is it.
DaveBaumann said:
I don’t care what ATI are claiming and whether or not it is a 130nm part, again I’ve not yet disputed that the EE+GS can be classed as 90nm – I’m just trying to establish the gate lengths of EE+GS because there appear to be contradictory evidence of that from the only source that has claimed 45nm gate lengths.
Oh, right, this again. I think I already addressed it like 100 times over the past year since the SI story broke. I can't make this any clearer, if you can't comprehend, then it's your problem:
<blockquote>It works like a production maximization curve Dave, you have an outer bound that's the minimum attanable gate length which yeilds the maximum preformance. You then, as in the production maximization example, can have data points
under the curve (but not beyond the bound). In the EE+GS's case wrt CMOS4 (which defines the bounding curve), they want to maximize productivity and yeilds (profits), which adds another dimension to the analysis and pushes the equilibrium point
from the edge. This means that their point of equilirium based on the variables they bias as important isn't found on the edge of the curve, it's found within somewhere. This means that only the few gates and constructs which require tuning recieve it, the vast majority forgo it and, instead, get a more manufacturable and yeildable gate which provides the necessary preformance level that's been fixed for 3 years since they reached the level in 2000 at 250nm.
But, what's noteworthy is that the process technology (CMOS4) and their manufacturing technology (ArF 193nm) is capable of producing a 45nm gate and
has mass produced gates of this size since mid-2003. All it takes is a
single gate to demonstrate the technology, the implimentation is a seperate issue dependant on many variables -- as I tried to get acoss in the ATI example but was lost in the frontal-lobe somewhere. </blockquote>
I really can't see any way around it for them, except locking people into long-term licensing contracts NOW. Eventually they will become passe.