[SONY PLAYSTATION 6]
>More or less continues traditional console design philosophy
>Comes with an Entry-level PSVR Gen 3 helmet for standard SKU
>Revised DualSense controller, now full VR-capable. Unique three-piece design, revamped haptics,
positional/motion/acceleration/proximity detection. Center piece usable as a room-scale calibration
and tracking module (extras can be purchased separately; wireless connection to mesh grid
network for expanded, scaled tracking)
>Significantly revamped OS for VR-native navigation, features, etc.
>Optional VR controls will also be available for users who prefer it
[CPU]
>CORES: 8 (CPU block 1), 8 (CPU block 2)
>THREADS: 16 (CPU block 1), 8 (CPU block 2)
>CLOCK: 5.2 GHz (CPU block 1), 5.2 GHz (CPU block 2)
>L1$: 64 KB (per core, CPU B1), 32 KB (per core, CPU B2)
>L2$: 1 MB (per core, CPU B1), 1 MB (per CCX, CPU B2)
>L3$: 8 MB (all, CPU B1), 4 MB (CPU B2)
>L4$: 8 MB (shared, CPU B1 & B2)
>>NOTES: CPU B2 is repurposed integration of PlayStation Stream CPU. PlayStation Stream CPU is more advanced (i.e features) processor vs PlayStation Fold, still 8C/8T design, lower-clocked in PlayStation Stream. Design necessary as PS Stream provides native play of PS4 titles requiring 8C/8T setup with similar L2$ and L3$ implementation.
B2 cores based on lower-scale Zen-ARM variants; have certain reduced functionality (reduced FP and AVX 256) vs. B1 cores that are based on regular design. Cores B1 & B2 operate in HMP (Heterogeneous Multi-Processing) Mode.
[GPU]
>ARCHITECTURE: RDNA
>GENERATION: 7
>PROCESS: N3P
>CONFIG: Chiplet
>SHADER ENGINES: 2
>SHADER ARRAYS (PER SE): 2
>COMPUTE UNITS: 40 (20 per Shader Engine, 10 per Shader Array)
>COMPUTE UNIT CONFIGURATION: Dual CU
>SHADER CORES (PER CU): 128
>SHADER CORES (TOTAL): 5120
>ROPs: 128
>TMUs: 8 (per CU), 320 (total)
>ALUs/SHADER UNITS: 5120
>STATE MODES (IF ANY): 2; FULL (40 CUs), HALF (20 CUs)
>CLOCK FREQUENCIES: 3901.396 MHz (FULL), 4659.96 MHz (HALF)
>IPC: 2
>IPS: 6724.427 million IPS (FULL), 9319.9236 million IPS (HALF)
>THEORETICAL FLOATING POINT OPERATIONS PER SECOND: 39.95 TF (FULL), 23.859 TF (HALF)
># PRIM UNITS: 4 (2 each SE, 1 each SA)
># PRIMs/CLOCK PER UNIT: 4
># TRI RAS/CLOCK PER UNIT: 2
>PRIMITIVES PER CLOCK: 16
>TRIANGLES PER CLOCK: 8
>GEOMETRY CULLING RATE: 62.422 billion (FULL), 37.279 billion (HALF)
>TRIANGLE RASTERIZATION RATE: 31.211 billion (FULL), 18.639 billion (HALF)
>PIXEL FILL RATE: 499.378 Gpixels/s (FULL), 298.237 Gpixels/s (HALF)
>TEXTURE FILL RATE: 1248.446 Gtexels/s (FULL), 745.5938 Gtexels/s (HALF)
>THREAD DEPLOYMENT RATE: 40,960 (FULL), 20,480 (HALF)
>CACHE CAPACITY:
>L0$: 16 KB per CU (640 KB total)
>L1$: 64 KB per dual-CU/WGP (1.28 MB total)
>L2$: 512 KB per Array (2 MB total)
>L3$: 16 MB
>TOTAL: 19.92 MB
>CACHE BANDWIDTH:
>L0$: 39.55 TB/s (FULL), 23.62 TB/s (HALF)
>L1$: 27.685 TB/s (FULL), 16.534 TB/s (HALF) (L0$ * .70)
>L2$: 16.611 TB/s (FULL), 9.92 TB/s (HALF) (L1$ * .60)
>L3$: 8.3 TB/s (FULL), 4.96 TB/s (HALF) (L1$ * .30)
>TOTAL: 88.829 TB/s (FULL), 55.034 TB/s (HALF)
[TASK ACCELERATION ENGINE]
**Heavily modified CU for various hardware-based RT, ML, IU, AI tasks
**Each Shader Engine is paired with a Task Acceleration Engine
**TAEs can house either 1 or 2 Task Acceleration Arrays
**TAAs can be of any given size when it comes to TAUs; however ideal
balanced designs generally call for TAAs that are 50% the core unit
count of a design's Shader Array (i.e a design with 5 Dual CU Shader
Arrays (10 CUs) having 5 TAU TAAs).
**TAUs can be thought of as pseudo-FPGA cores; each unit has internal
fixed-function hardware as well as a modified frontend compared
to normal CUs. TAUs also can range from having the following:
>2,000 To 8,000 logic cells
>16 Kb (2 KB) to 128 Kb (16 KB) distributed RAM (LUT) (acts as L0$)
>64 Kb (8 KB) to 512 Kb (64 KB) BRAM (acts as L1$)
>Internal Command Sync & Program Interface Configuration core
(directed by application to program the FPGA logic into
desired program state, manage unit state)
>Compute Thread Controller core (this is what programmers
interface with in dispatching code for the configured units
in the TAA to execute)
>1 Mb (128 KB) to 4 Mb (512 KB) SRAM (L2$, shared with all units in TAA;
meant for processed data locality storage)
>Shared 8 MB XIP (Execute-in-Place) Resource State Preset-allocated
MRAM (holds the microcode in bit-addressable/byte-addressable
format for immediate configuration)*
* = Will be able to be updated with future firmware changes
* = Shared between both TAAs
* = Simply used to configure the FPGA logic & fixed-function
aggregate unit states to specific profile presets (RT, ML, AI,
or IU) by storing the relevant set-up and configure/compile data
># TAEs: 2 (1 per SA)
># TASK ACCELERATION UNITS (TAU) PER TAE: 5
>LOGIC CELLS: 5000 (per TAU); 25,000 (per TAE), 50,000 (total)
>LUT RAM (L0$): 12 KB (per TAU), 48 KB (per TAE), 96 KB (total)
>BRAM (L1$): 48 KB (per TAU), 240 KB (per TAE), 480 KB (total)
>SRAM (L2$): 384 KB (per TAE), 768 KB (total)
>MRAM: 6 MB (total)
># CU: 1 (PER DUAL CU IN SA), 5 (PER SA), 10 (TOTAL)
>ARCHITECTURE: Tempest Audio (Tempest Audio Engine Next (TAEN))
>GENERATION: 2
>DSPs: 2
>PROGRAMMABLE LOGIC: 1
>Modified single CU core
>3.9 GHz (fixed clock)
>8 KB L0$, 32 KB L1$, 128 KB L2$DFD
>No L3$
>~ 1 TF (998.75 GFLOPs)
>Can leverage up to 40 GB/s of system bandwidth
[MEMORY]
>TYPE: HBM4E
>GENERATION: 1
>MODULE CAPACITY: 2 GB
>MODULE AMOUNT: 16x
>CONFIGURATION: 1X 16-HI
>I/O PIN BANDWIDTH: 6.2 Gbps (775 MB/s)
>I/O PIN COUNT: 128
>BUS WIDTH: 2048-bit
>MODULE BANDWIDTH: 99.2 GB/s
>TOTAL BANDWIDTH: 1587.2 GB/s (1.5872 TB/s)
>TOTAL CAPACITY: 32 GB
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