Oh. Unknown. That's a lot of eDRAM though.Apologies. I should have been more specific, I thought the 70+ was for the next Xbox.
Oh. Unknown. That's a lot of eDRAM though.Apologies. I should have been more specific, I thought the 70+ was for the next Xbox.
Bunk at this point. All the 'big' rumours were bunk. Wii U has no significant strengths. Other than size and power draw.
lol, I'm honestly shocked if anyone will use even 256bit membus, 128bit 99% surely since 256bit not only brings the costs up a LOT, but also means the chip must be so much bigger even when you shrink it
can sony put a hd 7970 ( a.k.a tahiti ) chip in ps4 but only using its 384bit bandwidth and 18 CU out of 32 ?
Why make things more complicated when there's easier ways? Why scale down when you can start down to begin with, uhm Pitcairn? But then it's likely too small for the required 384bit i/o pads, it would have to be tahiti size and no one would want to use 40% of their die for redundancy.
They could fill it up with CPU cores.But then it's likely too small for the required 384bit i/o pads, it would have to be tahiti size and no one would want to use 40% of their die for redundancy.
With an APU I don't see this as much of an issue. It's also far from certain that there'll be a shrink next gen, going to 20nm may end up being a cost instead of a cost saving.
At 128bit DDR4, that's 35-37 GBs BW which is only a 48% increase in BW. 128bit DDR3 is even less (28.5 GBs or 15%). With ROPs and TMUs likely to be at 4x current I don't see how it's even an option.
There's always GDDR5
What are TSV s and how can these be used in sony's ps4 ?
Fermi and half rate make a better example ... quarter rate is reasonably cheap.For example a console design would probably left out something like Tahitis quarter-rate-double-precision.
TSV = trough silicon via, or a process step that allows you to cut a communication path through the substrate of a silicon chip. This would allow you to bond a tower of chips where they all face the same way, as opposed to being forced to bond chips only face-to-face like we can at present.
TSV:s are probably not ready for any reasonable launch.
The kind of 3d stacking that people are more exited for the ps4 atm is using a silicon interposer, or a very large chip fabricated with a very cheap process that's placed at the bottom of the stack facing up, and then you can bind the rest of the chips on it facing down. You get the advantages of cheap communication lines, without the advantages of short distances. This is also often called 2.5d stacking.
HMC is achieved via TSV.
Lol xD
Why is MS in the HMC project? I know, I know, no possibilities of HMC in Xbox Next, but then, why is MS in HMC consortium?
From what I know of HMC the first applications that it will be rolled out in are servers. I imagine MS is involved for those applications first.
I'll speak more about what's happening in game consoles as well. A pretty good push for more memory coming up in the Game Console segment as a level of redesigns. We'll start to hit it over the next couple of years.
And talking about consumer again here. I thought it'd be beneficial to show you across a couple of key applications how this looks in terms of megabyte per system. On the left, what we have are game consoles. This is a space that's been pretty flat for a number of years in terms of the average shipped density per system. That's going to be changing here pretty quickly. I think everyone realizes that these systems are somewhat clumpy in their development. The next generation of system is under development now and that because of 3D and some of the bandwidth requirements, drives the megabyte per console up fairly quickly. So we're anticipating some good growth here.
We've worked with a number of these vendors specifically on both custom and semi-custom solutions in that space.