Predict: The Next Generation Console Tech
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And why? pretty cheap EDIT really/dirty cheap /EDIT DDR3 running at 1000MHz (2000MHz effective) provides 32GB/s.
You have two buses so it is in aggregate bandwidth 64GB/s.
DDR3 can go higher (like say 1333MHz) but I could see MS avoiding the premium of the most wanted memory chips on the market.
Then moving to the rendering I expect (assuming they make such a move) to enforce tile based deferred rendering with CPU assistance for binning, etc.
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An APU with a 6670?
ಠ_ಠ
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PS4 Rumours moved/merged: http://forum.beyond3d.com/showthread.php?t=61745
An APU with a 6670 doesn't sound too promising according to this review:
source
http://www.techradar.com/reviews/pc-mac/pc-components/processors/amd-a8-3870k-black-edition-apu-1057509/review/page:3#articleContent
I'm not sure of this review. As it is with limitation faced by pc gaming for compatibility sake, dual graphic mode comes with quiet some problem and is not that optimal. Using nowadays pricing one is better off with a athlon X4 cheaper than the APU and invest the difference in a better GPU.
For the memory controller lets hope AMD makes it better.
EDIT
The idea of two SoC is supported by Tim Sweeney, Epic is considered to have influence on MS choice and he said C.Demerjan that he would prefer twice the same chip if there were to be two chips that's it.
In regard to the CPU set-up power a2 is dirty cheap (in silicon cost) so I may prefer a beefier CPU.
Three cores, three issue, simple OoO execution, not too wide, 4way SMT, 256 bits wide SIMD (FP only), same support as the power a2 with regard to transactional memory, running @ ~2.4GHz, 512KB of L2 per core, lets call it an efficient but versatile number crusher.
With 2 units in the system that's around 115millions of CPU FLOPS (230 if speaking of multiply add, even more if there is a dot product instruction as in Xenon).
For the GPU GCN would be (obviously) welcome but if 32nm is used and looking at llano density... it may get costly.
For the memory controller lets hope AMD makes it better.
EDIT
The idea of two SoC is supported by Tim Sweeney, Epic is considered to have influence on MS choice and he said C.Demerjan that he would prefer twice the same chip if there were to be two chips that's it.
In regard to the CPU set-up power a2 is dirty cheap (in silicon cost) so I may prefer a beefier CPU.
Three cores, three issue, simple OoO execution, not too wide, 4way SMT, 256 bits wide SIMD (FP only), same support as the power a2 with regard to transactional memory, running @ ~2.4GHz, 512KB of L2 per core, lets call it an efficient but versatile number crusher.
With 2 units in the system that's around 115millions of CPU FLOPS (230 if speaking of multiply add, even more if there is a dot product instruction as in Xenon).
For the GPU GCN would be (obviously) welcome but if 32nm is used and looking at llano density... it may get costly.
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After all the praise XB360's UMA got, there's just no bloody way they'd go separate pools now
http://www.gamesindustry.biz/articl...ess-powerful-than-ps3-xbox-360-developers-say
I really doubt this because it would need effort even from Nintendo. But it really is looking to be in the 300-500Gflops range based on winks and hints
I really doubt this because it would need effort even from Nintendo. But it really is looking to be in the 300-500Gflops range based on winks and hints
Ten to one that vg247 pulled the entire story out of their collective arses.
Reserve a core for kinect? Why? What about games that don't feature Kinect, or only feature voice commands. And reserve a core for the OS? What background OS task could possibly take up an entire modern CPU core?
Cheers
Reserve a core for kinect? Why? What about games that don't feature Kinect, or only feature voice commands. And reserve a core for the OS? What background OS task could possibly take up an entire modern CPU core?
Cheers
Every generation is different. There are always different pressure points and inflection points.
Just noting that because, "It didn't go over well last gen" isn't always a good metric for a new platform. Have the pressures and market realities changed?
Not saying they have but I think you could at least toss out one theoretical way where a Split Memory Architecture, ala PC, could trump a UMA: UMA means all your memory is the same. In most cases that means you either need really expensive memory or are going to have poor performance. But what we see on the PC is the CPU have different tolerances and there is a cost spread in memory. So using the "PC" model you could go with 6GB of DDR3(4) for the CPU and 2GB of fast GDDR5 (or specialized architecture) *vs* the UMA which would be a crazy expensive 4GB of GDDR5 or, gasp, slower GDDR5 -- and the kicker is the 4GB is going to cost as much as the 8GB. And while it would be nice to have one memory pool having more stable memory performance patterns is a plus and the question is: will a console GPU be "using" 4GB of memory? Not that the system cannot, but the GPU specifically? Would it perform better with 2GB of fast memory + 4GB of cached video data sitting in main memory?
I have also always wondered about the logic that in VRAM you may, as an example, at times only have 10-20% of your data being actively rendered but that data is soaking up 90% of your VRAM bandwidth. Basically a small footprint client sucking up the entire source. Throw that into an UMA and you have an even smaller percentage of asset sucking up all system resources. This is one area where the eDRAM made sense (it offloaded an expensive part of the graphic budget + made for a more regular bandwidth consumption pattern from the UMA).
Again, I am not shooting down the prospects of an UMA, only that things change. If for the same cost of 4GB of GDDR5 you can get 6GB DRR3 and 2GB of GDDR5 you create a very interesting scenario.
I was thinking, or at least hoping, the same thing. A whole core reserved for the OS and Kinect sounds like a complete waste. How do they go from a fraction of cores 0 and 1 on the 360, to an entire core on the 720? Also as you said, why reserve an entire core to Kinect when there could be games that never use Kinect.
We have many, many devs saying it's from "more powerful" to "far more powerful" etc compared to PS3/XB360 already, this is quite surely just bollocks "news" (though I have a feeling few people here, too, will believe just because it says Nintendo is making low horsepower console)
IllusionistK
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PlayStation 4: Sony “confident” of pre-Xbox 720 release
http://www.vg247.com/2012/04/02/playstation-4-sony-confident-of-pre-xbox-720-release/
http://www.vg247.com/2012/04/02/playstation-4-sony-confident-of-pre-xbox-720-release/
You aren't going to get a finer range than the PS vs 360 that are arguably almost completely equal.
It is very likely to be a bigger difference next gen, by chance if nothing else.
Stereoscopic 3d comes across as having enormous potential for Kinect. Imagine a custom dashboard for Kinect users with stereoscopic displays.
I wouldn't be suprised if Microsoft teams up with LG to push some OLED displays with passive stereoscopic. With passive the glasses are very lightweight. They worked with LG in the past already.
I could see Microsoft releasing a high end "Stereoscopic Sku" for those that want to game at at full frame rate and resolution. Maybe a $699 release point.
So you would have
$399 base console
$499 hard drive console
$699 dual gpu stereoscopic console with Kinect 2.0
Far more powerful would mean that box would sound worse than a hoover at 1200W.
But in reality Wii U will make little to no sound at all just like Wii which means it´s not generating much heat
Well you missread my post I'm speaking of a coherent memory space
It would be pretty much like in bi processor set-up or a cell blade for that matter both physical partition of the ram are acessible to both processors.
All you need is a fast link (not that fast) between the two processors thatsupport coheremcy traffic (on top of data traffic).
The most recent official quotes from developers had been shady: "on par with current gen", "pretty powerfull" (wich means nothing) etc.
So maybe WiiU hardware had been downgraded since last year, to keep the low cost or something. Maybe Nintendo will release 199$ console, who knows
So maybe WiiU hardware had been downgraded since last year, to keep the low cost or something. Maybe Nintendo will release 199$ console, who knows
about VG247's nextbox rumor,i find something interesting from that 2011 Dec's pastebin article
http://pastebin.com/j4jVaUv0
"The XB3 will also have a 24/7 connectivity system which has not been entirely elaborated on"
so,maybe media is copying this article every month to make a new rumors(lol),or maybe this article is true in some point after all
http://pastebin.com/j4jVaUv0
"The XB3 will also have a 24/7 connectivity system which has not been entirely elaborated on"
so,maybe media is copying this article every month to make a new rumors(lol),or maybe this article is true in some point after all
Speaking of throughput oriented cores I thought of an "old" IBM patent somebody linked in those pages a long time ago (maybe years) if memory serves right the thing was about a core to which 2 vector units were attached that could act independently or as a wider one.
So I may correct my pov about a possible xenon2 and instead of a 8 wide SIMD the thing would embark 2 4 wide SIMD. It may look the same but it is not. Xenon SIMD were not really multi-threaded so if two threads executed on it behaved as 2 simd working at half the speed (I guess only one instruction at a time could be issued to the SIMD unit).
That would not be the case with 2 SIMD units.
If we have a 3 issue CPU I wonder if it could prove a better usage of the chip resources.
If you have more integer work you may use the 2 SIMD as one (so less instructions are issued to the SIMD) or not at all so letting more instruction to be issued on the integer pipe and so letting the OoO engine exploits ILP.
If the workload is SIMD heavy the integer pipeline and the front end ( more complex than in xenon) is amortize on more than one unit, a bit like the scalar unit in last AMD gpu.
As I see those throughput cores only the scalar/integer part would allow OoO execution, its cost in hardware (ooo engine, the front end can issue more instructions, LSU, AGU, ALU) could be amortized on two simd units.
It may not make sense but definitely more insights are welcome. It would be some sort of reverse BD, in BD the expansive and extremely complex front end is amortized on 2 cores, here the cost of having 2 SIMD is lessen by a shared scalar/integer pipeline which (vs something as Xenon or power a2) would have been improved.
Using a simple image with Xenon as a ref, the new core dealing with the same two threads as a Xenon one would get the job done twice as fast. Say those threads are a mix of SIMD and integer instructions, now each thread has it own SIMD unit working for it at full speed and the beefed up integer pipeline may provide enough performances to not bottleneck the vectorized part of the code.
I would see the core supporting 4 way SMT, so per cycle the new core would do the job of 2 xenon cores. It would not come close to the improvements a bulldozer core would bring in single thread performances but if the cpu is used for quiet some number crushing it could be a good trade off: *improved single thread performance (still nowhere near x86 high cpu)
*beefy increase in Sustained throughput
*down to the silicon it's likely to be cheaper and more efficient than having 2 full blown cores.
*as SIMD units may not want to load or store data at the exact same time, it may be easier to efficiently feed 2 4 wide units than a 8 wide one (?)
Assuming 6 of these cores throughput per cycle would be 4 times Xenon throughput.
It could better in real term if those cores are backed by more caches, providing lower latencies, with more bandwidth to the main ram, improved branch prediction, etc. / fixing xenon big weaknesses.
Lowering clock speed to say 3/4 of xenon so 2.4GHz it's still a x3 increase in throughput (and more) that's a lot cpu power. For programming pov the thing would be handled as a bigger/better xenon, to use a dumb picture more as an IO++ CPU than as your standard wide OoO cpu.
PS:
I had no access to PC yesterday night for personal reason and posted on my phone which proved difficult, thanks to the moderation for allowing me to do so
I hope that my post were not that bad of a mess so
So I may correct my pov about a possible xenon2 and instead of a 8 wide SIMD the thing would embark 2 4 wide SIMD. It may look the same but it is not. Xenon SIMD were not really multi-threaded so if two threads executed on it behaved as 2 simd working at half the speed (I guess only one instruction at a time could be issued to the SIMD unit).
That would not be the case with 2 SIMD units.
If we have a 3 issue CPU I wonder if it could prove a better usage of the chip resources.
If you have more integer work you may use the 2 SIMD as one (so less instructions are issued to the SIMD) or not at all so letting more instruction to be issued on the integer pipe and so letting the OoO engine exploits ILP.
If the workload is SIMD heavy the integer pipeline and the front end ( more complex than in xenon) is amortize on more than one unit, a bit like the scalar unit in last AMD gpu.
As I see those throughput cores only the scalar/integer part would allow OoO execution, its cost in hardware (ooo engine, the front end can issue more instructions, LSU, AGU, ALU) could be amortized on two simd units.
It may not make sense but definitely more insights are welcome. It would be some sort of reverse BD, in BD the expansive and extremely complex front end is amortized on 2 cores, here the cost of having 2 SIMD is lessen by a shared scalar/integer pipeline which (vs something as Xenon or power a2) would have been improved.
Using a simple image with Xenon as a ref, the new core dealing with the same two threads as a Xenon one would get the job done twice as fast. Say those threads are a mix of SIMD and integer instructions, now each thread has it own SIMD unit working for it at full speed and the beefed up integer pipeline may provide enough performances to not bottleneck the vectorized part of the code.
I would see the core supporting 4 way SMT, so per cycle the new core would do the job of 2 xenon cores. It would not come close to the improvements a bulldozer core would bring in single thread performances but if the cpu is used for quiet some number crushing it could be a good trade off: *improved single thread performance (still nowhere near x86 high cpu)
*beefy increase in Sustained throughput
*down to the silicon it's likely to be cheaper and more efficient than having 2 full blown cores.
*as SIMD units may not want to load or store data at the exact same time, it may be easier to efficiently feed 2 4 wide units than a 8 wide one (?)
Assuming 6 of these cores throughput per cycle would be 4 times Xenon throughput.
It could better in real term if those cores are backed by more caches, providing lower latencies, with more bandwidth to the main ram, improved branch prediction, etc. / fixing xenon big weaknesses.
question to knowledgeable members if the scalar/integer pipeline is OoO wouldn't that fix LHS issue? I mean load and store units are considered part of the scalar/integer pipeline right? so Load and store are executed out of order
Lowering clock speed to say 3/4 of xenon so 2.4GHz it's still a x3 increase in throughput (and more) that's a lot cpu power. For programming pov the thing would be handled as a bigger/better xenon, to use a dumb picture more as an IO++ CPU than as your standard wide OoO cpu.
PS:
I had no access to PC yesterday night for personal reason and posted on my phone which proved difficult, thanks to the moderation for allowing me to do so
I hope that my post were not that bad of a mess so
Last edited by a moderator:
Is it in the realm of possible that IBM and AMD work together on an APU, sharing their newest design? It's a bit different situation that the partnership for designing the Xbox360 SoC, were both AMD graphic architecture, and IBM core architecture were obsolete.
Putting together 2 rumors: 6 cores are heavily modified Power7/Power8 cores, 2 cores are high-throughput SIMDs, designed by IBM, no ROPs, no TMU, with OpenCL/DirectCompute capability.
Putting together 2 rumors: 6 cores are heavily modified Power7/Power8 cores, 2 cores are high-throughput SIMDs, designed by IBM, no ROPs, no TMU, with OpenCL/DirectCompute capability.
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