Wow I missed that, I wonder if it is completely about price/BOM or about stark segmentation Intel style though.
Maybe both? One thing that nVidia might be considering is that a 256-bit GDDR5X device might salvage into a lower performance GDDR5 part without leaving any of the 256-bit interface unused (while it might if the top end part used a 384-bit GDDR5 arrangement). That way you hit performance and market targets while minimising die area for all parts.
Why?
I mean "top end" relative to its bus size . For example most 128-bit devices might use GDDR5, but the top end 128-bit device might use GDDR5X to hit a higher performance level and move into the gap below the entry level 256-bit device, while potentially still using less power.
I like the idea of a south bridge having many GBs of really cheap ddr3 on a 32bit bus, for the purpose of a managed IO buffer, preloading assets. Instead of wasting expensive gddr5 for it.
Yup. That's one of the reasons I liked the idea of HBM and DDR4, though as you say if the render is accurate that doesn't appear to be the case.