AMD Vega Hardware Reviews

Discussion in 'Architecture and Products' started by ArkeoTP, Jun 30, 2017.

  1. ECH

    ECH
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    Indeed they can with AMD cards. Never understood why that was. When a reviewer tests for themselves no problem is found. I found that increasing the font size of the OSD did impact my performance. Might have just been squirrely on my end but I did see fluctuations move the font size slider back and forth while in game.

    However, I did come across one you tuber who did see something odd with AMD performance and found the trigger to be sleep mode.



    So the "fix" is to not use sleep mode right? Not so fast! Although not mentioned in the video if you enable "fast boot" from the bios you are essentially doing the same thing in Windows 10. Do you find it hard to believe? Open Task Manager then tab over to Performance and look at your Up Time. If you use fast boot your Up Time will show several days that your PC has been up. Even though you've pushed the off button daily.

    The fix is to disable fast boot and, or sleep mode until AMD fixes the issue with degrading performance in sleep mode. I hope they are instructing reviewers of this in their press release docs.
     
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  2. itsmydamnation

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    Hi Raja? Lisa ?
     
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  3. digitalwanderer

    digitalwanderer Dangerously Mirthful
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    Pissed about Raja, REALLY not sure what Lisa is thinking/planning/doing, and not sure at all what is going to be happening going forward. I won't lie, I'm freaking clueless. I tried putting all the pieces I have together and I just can't find a way they fit properly, I'm still missing too many pieces and I doubt I'll ever find them.

    I'm really curious to see what happens next, I really am. It's been a long time since I felt so in the dark about what happens next that it's almost nostalgic! :)
     
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  4. itsmydamnation

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    I expect Navi to have just as much if not more uarch change as vega did. I dont know if AMD will recover the performance deficit with navi, but i dont think thats the end of the world if they dont either.
     
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  5. Jawed

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    Probably a question for the Navi thread: what if everything Navi needs is in place?

    One of my pet theories is that AMD, at GF, doesn't really care about die area: due to the wafer supply agreement, die space is at a huge discount. So spend it in Vega in preparation for Navi?
     
  6. Alexko

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    I'm a bit confused. Setting aside the validity of the premise for a moment, how would that work?
     
  7. Jawed

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    Vega is this honking fatarse die. When you cut it up into chiplets, because that's my theory of Navi, that fat is part of what makes the chiplets work together - it's the overhead associated with disaggregation. So I infer that Vega is the vehicle to research the chiplet approach, which includes blubber no one can otherwise explain.
     
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  8. 3dilettante

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    AMD is obligated to purchase a certain volume of wafers per quarter, and will be paying some kind of charge regardless of whether its quota is fulfilled. In the absence of any other demand, using up volume for some kind of product would be better even if it is doing so less efficiently.

    Counter to this, the x86 segment's uptick in sales and that portion's general dominance of AMD's financials serves as a form of internal competition to a discrete GPU, and it's not clear how much capacity would be left over.
    AMD's negotiating for being able to pay for "certain products" to be fabbed elsewhere for capacity or other reasons has historically been an x86-related exemption that might point to what AMD projects is the more significant consumer.
    Vega's ability to create demand may be subject to AMD's ability to get volumes for other components like HBM2, which might limit its ability to use up wafers as well.

    (edit: added quote @Alexko )
     
  9. Alexko

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    I'm aware of the WSA, but as far as I know, the precise amount AMD is committed to purchasing is unknown. Therefore, whether they actually have spare "free" capacity is dubious. Besides, as I remember, there were penalties for under-ordering, but the penalties were somewhat lower than the price of the wafers not ordered, so it's more like "cheap" capacity than free.

    But the question is: supposing that AMD does have cheap/free capacity, what can it add in Vega that somehow prepares for Navi but brings nothing tangible at the moment? In what way would it make developing Navi easier or faster? I'm not being argumentative here, it's an actual question.
     
  10. 3dilettante

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    I do not recall what the latest agreement does, or how its costs for going over or under GF's limit would show.
    Prior to that, the regular negotiations, disclosures of shortfall penalties, and scheduled payments did show for AMD.

    As long as AMD doesn't sell a die for less than that discounted price+overhead, it would seem like it would be better than a loss with no compensating revenue.

    The one area that stands out is a strip of the die between the ROPs and HBCC that AMD outlined as being part of the infinity fabric's domain. The wafer shots do not have detail to show whether there's I/O that could be used to connect to another chip. It's possible that there's something too blurry to see, or a reuse of PCIe, otherwise I'm not sure there is any tangible benefit.
    That fabric is also something that Koduri apparently stated was more "server-oriented" on twitter/reddit, and that a client-optimized variant could happen. What that means isn't clear, since Vega 10 has lost high-end features like on-die ECC and higher FP64 throughput.
    That area is rather modest, however.
    It seems like Vega gives around 3/4 of its area to the GPU proper, which is slightly less than Fury's percentage. Other consumers of area, such as the page-management hardware of the HBCC or the on-die flash controllers have other uses or do not help an MCM.
     
  11. digitalwanderer

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    Wow, that sort of makes sense to me and fits pretty well. Thanks Jawed, I think you gave me another little piece! :D

    Next question, think Intel might now be taking a chiplet approach now that they have the mad scientist who included all the blubber to figure it out with or would that be an IP infringy-thingy or could they just rename it 'hyper-chiplets' and get away with it?

    Thanks again, you really got my brain humming in a bit of a new directions now and looking at what they're NOT using on the Vega or what doesn't need to be there is suddenly something I wanna go check out really badly. :D
     
  12. ECH

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    AMD Investor Presentation is worth a good read.
    http://phx.corporate-ir.net/phoenix.zhtml?c=74093&p=irol-irhome


    It appears they are finally referencing the Radeon RX as "For Enthusiasts". That's rich! As it was never mentioned as an Enthusiasts card before. It was only referenced as "High End" which is a step below Enthusiast level. Which the RX64 clearly shows in numerous reviews against a 1080TI. Also, clearly shows to win/loss against a 1080 which is also High End, not Enthusiast level card.

    So what are we looking at here in this Investor Presentation? Is this slick marketing alone or are we looking at something of what's to come? From what I've read, it looks like we are headed toward a die shrink. According to AMD's road map 7nm around 2020. I wonder if Vega and Polaris (which is in page 10) is headed for die shrinks in 2018. Or, being revamped right now for tape out?

    Since they have Polaris as part of their 2018 lineup (12/10nm) I wonder if these small die will make up Navi mGPU iFab package?

    If Vega is getting a die shrink then I can only perceive this as a clock rate increase.
     
  13. 3dilettante

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    AMD's particular usage of the term chiplet is centered around a doubling-down or perhaps tripling-down on 2.5D or 3D integration with silicon interposers.
    A chiplet in AMD's parlance is a piece of silicon that contains IP functionality that cannot function in the absence of an active silicon interposer underneath that provides part of a NOC.

    Intel's plans may include separating out die sections, but its reluctance to embrace even passive interposers and EMIB's purpose in avoiding them puts Koduri's starting position further from where he might have been going with AMD.

    That he left might be a sign of where AMD's plans are. There aren't many disclosures or specific claims for what AMD intends to do to make their chips work together. Hand-wavy exascale aspirational papers, some possibly-contradicted internal slides, and some patents are out there. Much of it is relatively blue-sky or long-term DOE program work, and a lot of it is significantly more complex to make practical than interposer-based GPUs and rehashed DVFS AMD is making limited impact with.

    If there are specific implementation details to AMD's maybe-architectures, perhaps Intel doesn't have full access to them like it would with ISA or on-die architectural elements--assuming Intel wants to do what AMD does.
    I'm leery about assuming AMD does. I'm of two minds as to the limited predictions made for AMD. I'd found Koduri's description of future scalability with multi-chip to be rather low-rent, but AMD's HPC chiplet promises equally vaporous.

    I'm not sure how much of any of that was due to secrecy, a lack of actionable near-term milestones, CPU/GPU group drama, lack of resources/hope, or disparate visions.
     
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  14. Alexko

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    Didn't AMD say that they'd spent a lot of transistors on enabling higher clocks?
     
  15. Anarchist4000

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    I'd think margins and constrained supply in the face of Ryzen makes more sense here. Ryzen receiving preferential fab allocations. HBM2 could also be a factor, but competition from Ryzen seems more likely. One point may be that now that Vegas are becoming more available, Ryzens are possibly seeing a price cut. That could indicate a Fab constraint..
     
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  16. Anarchist4000

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    That was largely in reference to instruction caches. Cache in general being rather dense.
     
  17. digitalwanderer

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    I'm not sure if there really is a technical distinction between "high end" and "enthusiast level", I think they're more marketing buzz terms and to be honest I always thought of the Vega56 as an enthusiasts card since it delivers a level of gaming that a gaming enthusiast would enjoy. I'm not comparing it to any other card here, just the Vega56 in isolation, the latest nVidia card I've tried is what I'm using now a really sweet EVGA 680 GTI so I have no doubt the 1080 also delivers "enthusiast level" gaming quality...but I'm pretty sure the 1070s could too.

    Terms like this are sort of dumb imo, at least arguing about them unless they have some specific meaning. It's like "cutting edge" or "future proof", more buzzwords than anything else.

    I could be wrong and there is actual market segmentations broken down by these categories, but I'm not aware of any.
     
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  18. Jawed

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    Yes. GF might be worse than TSMC which is why the higher clocks (only slightly, compared with Polaris) are barely noticeable in the end product and power is such a nightmare...

    It's worth remembering that this is the biggest of the consumer dies on a node smaller than 28nm, bigger than GTX1080Ti. "Same compute", worse power, worse graphics performance - there's a lot of die "doing nothing" (when measured against NVidia) for an architecture that's supposed to be more efficient than older GCNs.

    I suppose it's worth remembering that there were quite a few franken chips during HBM development, chips that never became products. That would tend to contradict my theory of Vega being a test for disaggregation.

    We never really understood why there's so much memory on die. While memory doesn't take much area, a resolute memory architecture is important for a chiplet based architecture, because coordinattion amongst chiplets has communications overhead... There have been some odd performance results (mostly in synthetics) which raise questions about the memory architecture. If those results are valid, though, what with questionable driver immaturity. What if that performance was a reflection of a chiplet-type memory hierarchy

    Something doesn't add up, but there's little to work with. In the end my theory is just speculation for the sake of it.
     
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  19. ECH

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    Oh course what you say is sound in that regard. I guess the ambiguity of the term is a mildly agitating to say the least.
    I did recall this slide from a press release back then.

    [​IMG]

    They called it High-End. Sure it maybe "marketing" but to some of us that actually does mean something.

    But then I came across this:
    https://www.tweaktown.com/news/58037/amds-next-gen-navi-40-faster-rx-vega/index.html



    Here is something else of interest.
    [​IMG]

    Here they actually consider Navi as a "Performance Increase" while they don't really give Vega any real designation, for example Enthusiast or High End for that manner. Which makes me believe that Vega was just entry level Arch. paving way for Navi. Be that true or false remains to be seen. We know that they are going for Globalfoundries 7LP (Leading-Performance) process in 2/H2018. Refresh my memory does 7LP really mean anything regarding performance?

    I'm not sure if that will be limited to just Navi though. I wonder if they will test drive 7LP with Vega and Polaris?
     
    #1779 ECH, Nov 21, 2017
    Last edited: Nov 21, 2017
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  20. 3dilettante

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    I saw references to larger instruction buffers, which are not the same as the caches. I think some patches may have referenced an increase along the lines of moving from 12 entries to 16. Overall the only clear change I saw in this regard was that the front end would be shared with at most 3 CUs, rather than up to 4 in prior chips.

    The reference I saw where most of transistor count increase went:
    https://www.anandtech.com/show/1168...-vega-64-399-rx-vega-56-launching-in-august/3
     
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