Could this be related/impacted by the disabled DBSR? Honest question, I have no idea, but DBSR is related to rendering so...
Did you notice that the information about IPC came immediately coupled with FP16, RPM and INT8? I actually did and Anandtech as well:
"That said, I do think it’s important not to read too much into this on the last point, especially as AMD has drawn this slide. It’s fairly muddled whether “higher IPC” means a general increase in IPC, or if AMD is counting their packed math formats as the aforementioned IPC gain."
I was not expecting higher IPC in all situations. Why? Because if you look at the slide the difference is having two ops instead of one, which for me was a blatant clue that that was referring to RPM. The message was poorly conducted but the image was very revealing.
Given that Vega is still pretty much GCN, plays by its rules and limitations (e.g. maximum of 4 ACEs) and still has 4096 "cores , yes your expectations were too high. Especially when the same number of cores is now responsible for more geometry stuff than before. Didn't you think that that would have a drawback? The same number of units of Fiji but now spread out to more workloads would magically find a way to do more with same, even if running at higher speeds? If you didn't think a drawback would exist, yes that's silo vision because you were thinking about the changing in geometry without thinking about the impacts elsewhere.
I'm starting to think that's the reason for our disagreement. I had my expectations way more in check. It's performance is pretty much where I expected it to be.
That's the job of marketeers. I learned a long while ago the art of smelling bullshit and critical thinking about what they present, not taking anything they say at face value. As you can see from what I wrote above my expectations were balanced by this attitude.
Honestly, the White Paper is not that different from the slides, with the exception of not mentioning IPC anywhere. I guess they realised the stupidity of calling RPM an increase in IPC, which is really what they meant by it. Regarding reasonability of thinking, refer to my answer above about expectations.
Like I said above, it's still GCN. You don't just change how an architecture performs in every single situation overnight just with small tweaks and touches here and there. That's what Vega is, there was not a big overhaul, with the exception of RPM and INT8 which are more due to AI than gaming. Especially when the chip still has the same number of units. With the exception of Pascal consumer, NVIDIA always changed the SM layouts and unit ratios affecting load balancing from Fermi to Kepler and Kepler to Maxwell, looking for optimal performance. I had thought that by now, with 3 iterations of GCN, people would have realised that GCN does not offer the same kind of flexibility NVIDIA architectures have.
Refer to my point about the changes in geometry using more compute resources having a knock out effect on other functions that also use them.