Second Gen Cell info

[j^aws]

You would expect another set of VMX register blocks i.e another 'two' of those blocks for a 2nd VMX unit?

why want 2 VMX units?) full vmx size is big, 1/3 PPE size
with 2 thread and 2 multiply-add units you feel as if you have 2 VMX units
this design is cheap, and there 8 SPE

Bah! ...It's just more like the G5, i.e. 2* FPU units and a 4-way SIMD VMX unit...

Good but no CIGAR!

 

[version]

refresh

 

[Tacitblue]

The floating point block at the bottom is double precision too, exact same appearance as the DP unit on each SPE.

 

[j^aws]

refresh

I still see,

1 VMX unit
1 FPU unit
1 INT unit

 

[version]

refresh your browser!

 

[Panajev2001a]

You would expect another set of VMX register blocks i.e another 'two' of those blocks for a 2nd VMX unit?

why want 2 VMX units?) full vmx size is big, 1/3 PPE size
with 2 thread and 2 multiply-add units you feel as if you have 2 VMX units
this design is cheap, and there 8 SPE

I do not see 2 full Vector FMADD (two VALU as this is what we find in the VMX unit and this holds the Simple and Complex Fixed-Point as the Floating-Point Hardware) units in there especially sharing the same register file (32 registers for 2 VFPU would not be enough).

 

[j^aws]

refresh your browser!

That's what I said last page...Pana confused me even more!

That TWO IDENTICAL VMX units!

Both the VMX units can sustain a thread each, right?

 

[Panajev2001a]

refresh your browser!

That's what I said last page...Pana confused me even more!

That TWO IDENTICAL VMX units!

Both the VMX units can sustain a thread each, right?

Two VMX units feeding on a single 32x128 bits Register File ?!? I do not buy that.

 

[j^aws]

refresh your browser!

That's what I said last page...Pana confused me even more!

That TWO IDENTICAL VMX units!

Both the VMX units can sustain a thread each, right?

EDIT: Saw Pana's reply above...

@ Pana, they look identical though?

 

[j^aws]

refresh your browser!

That's what I said last page...Pana confused me even more!

That TWO IDENTICAL VMX units!

Both the VMX units can sustain a thread each, right?

Two VMX units feeding on a single 32x128 bits Register File ?!? I do not buy that.

I see the following registers,

2*32.128 bit VMX
2*32.64 bit FP
2*32.64 bit INT

Do you agree?

 

[version]

Two VMX units feeding on a single 32x128 bits Register File ?!? I do not buy that.

there 2*32*128 bit register file

 

[Tacitblue]

Just reiterating what was explained far earlier in the thread on the changes between the prototype and the production, there are twice as many of those particular units, be they VMX or whatever.....and the DP floating point unit in both iterations of the PPE is identical to the SPE's. I blocked out the clock and the test/pervasive section on the old die as it had moved beside the L2 on the newer model, just to emphasize the difference in die space there is.

 

[rendezvous]

I see the following registers,

2*32.128 bit VMX
2*32.64 bit FP
2*32.64 bit INT

Do you agree?

Me too, given the size of those register blocks compared to the ones in the SPEs which we know are 128x128bit.

 

[j^aws]

I see the following registers,

2*32.128 bit VMX
2*32.64 bit FP
2*32.64 bit INT

Do you agree?

Me too, given the size of those register blocks compared to the ones in the SPEs which we know are 128x128bit.

Then that would mean 2*VMX units can sustain 2 threads, right?

 

[Carl B]

Well this is all very good news for Cell - I'm excited to see what future variants and revisions might add to the mix. Taking this into account though, does that change any predictions on the sort of tech that might be making it's way to 360's tri-core then? It doesn't seem unreasonable that Microsoft might pursue a similar angle; would there be a larger drawback to their doing so than the PPE implementation in Cell? Obviously their die size would suffer more than the Cell, but would that be enough to prevent anyone from pursuing that course?

 

[j^aws]

Well this is all very good news for Cell - I'm excited to see what future variants and revisions might add to the mix. Taking this into account though, does that change any predictions on the sort of tech that might be making it's way to 360's tri-core then? It doesn't seem unreasonable that Microsoft might pursue a similar angle; would there be a larger drawback to their doing so than the PPE implementation in Cell? Obviously their die size would suffer more than the Cell, but would that be enough to prevent anyone from pursuing that course?

Expect the Xenon cores to have larger registers, i.e. 128.128 bit instead of 32.128 bit in CELLs PPE.

This also creates this range,

2 cores with 2MB cache <---> 3 cores with 1MB cache.

 

[McFly]

On the cell thermal image, the PPE was the hottest part, so just doing the same on the xbox 360 cpu would make the chip extremly hot I guess.

Fredi

 

[Carl B]

Expect the Xenon cores to have larger registers, i.e. 128.128 bit instead of 32.128 bit in CELLs PPE.

This also creates this range,

2 cores with 2MB cache <---> 3 cores with 1MB cache.

Thanks Jaws. I guess what I'm primarily wondering though is what sort of VMX spread we might be looking at inside the individual 360 cores. I wouldn't have expected two for the Cell PPE, and now I'm wondering if something unexpected might lurk in the tri-core as well.

 

[Carl B]

On the cell thermal image, the PPE was the hottest part, so just doing the same on the xbox 360 cpu would make the chip extremly hot I guess.

Fredi

Good point, but I think that the tri-core being clocked lower will probably help out with that.

 

[j^aws]

Expect the Xenon cores to have larger registers, i.e. 128.128 bit instead of 32.128 bit in CELLs PPE.

This also creates this range,

2 cores with 2MB cache <---> 3 cores with 1MB cache.

Thanks Jaws. I guess what I'm primarily wondering though is what sort of VMX spread we might be looking at inside the individual 360 cores. I wouldn't have expected two for the Cell PPE, and now I'm wondering if something unexpected might lurk in the tri-core as well.

If the above is true, (Pana, can you concur?)

PPE ~ 2 VMX units + FPU + INT

Then I'd expect each Xenon core to have 2 VMX units per core. However we may see 2 cores (4 VMX units) with 2MB cache instead of 3 cores (6 VMX units) with 1 MB cache. In fact the first option seems a larger die...

However, we are still looking at 2-way SMT per core...