Second Gen Cell info

[j^aws]

That's what i get if i count like you do.
Question is if we can count like that, 36 registers per thread seems somewhat odd.

That is unless Program Counter and/or status registers are stored in the regiser bank but if that is case, why aren't they stored in the register bank in the SPE?

edit: spelling and/or grammar.

I might have to dig up those CELL patents again but IIRC, those extra registers sound like the 'status' bits tracking threads running on the SPE's...?

 

[rendezvous]

Dig away, i'll stay as far away from patents as possible.
I still haven't found a way to decipher them that isn't painful.

 

[Tacitblue]

Well, post E3 seems to be a good time to dig this up, would it be fair they loaded the PPE core up with more units because they knew they'd be losing an SPE for producability reasons?

 

[Acert93]

Do we know if the PS3 CELL is the 1st (234M transistors) or 2nd (250M) revision?

 

[Tacitblue]

That's the funny thing, they showed the DD1 die and stated the DD1 transistor count at the press conference, who knows which variant it really uses. The disparity between the FLOP figures of what they mentioned before and what was stated at E3 would seem to suggest the opposite, that despite losing an SPE, that PPE core was pushing out plenty of power itself adding considerably to the final total of 218 GFLOPS. Turns out the PPE, whichever version it is, puts out roughly 39 GFLOPS@3.2Ghz. At least that's according to my fuzzy math. Which puts a non crippled Cell at almost 243.6 GFLOPS at the same clock. The producability of the units must be less than desirable. Hopefully fixable later.