IBM backstabbing sony and neglected Apple ? (long read)

Edge said:
Sorry, but this is just nonsense.
Yep.

I think IBM had interest in using the basic PPE core in other projects and it's exclusivity to Cell was never in play.

One thing that isn't mentioned is the switch from DD1 to DD2, a core which is strikingly similar to the Xenon core. If IBM was just content to milk Sony they wouldn't have switched to the new design, instead you can see that improvements to the design were transferred to all the clients.
 
Fafalada said:
At least the VUs had a decent instruction set.
Thanks to MS and Sony going with IBM we're now all stuck using crapped "real man's" SIMD for the next 5 years.
People bitch about lack of OOOe in the new CPUs - yet that was never really there in the first place. Meanwhile SIMDs have actually taken a massive step backwards from previous generations, and that's somehow supposed to be alright.

Really? Could you elaborate a little Faf... probably a lot, sorry. I'm surprised that VUs actually have a better instruction set than IBM SIMD. What exactl do you mean by "real man's" SIMD? Sorry, if it's a pain to explain, as much as you feel like is fine.
 
Fafalada said:
At least the VUs had a decent instruction set.
Thanks to MS and Sony going with IBM we're now all stuck using crapped "real man's" SIMD for the next 5 years.
People bitch about lack of OOOe in the new CPUs - yet that was never really there in the first place. Meanwhile SIMDs have actually taken a massive step backwards from previous generations, and that's somehow supposed to be alright.

Personally I thought the VU implementation was already a step backwards from the Dreamcasts SH4 SIMD......

So Maybe it's a trend :p
 
Fafalada said:
At least the VUs had a decent instruction set.
Thanks to MS and Sony going with IBM we're now all stuck using crapped "real man's" SIMD for the next 5 years.
People bitch about lack of OOOe in the new CPUs - yet that was never really there in the first place. Meanwhile SIMDs have actually taken a massive step backwards from previous generations, and that's somehow supposed to be alright.

I would assume that th present featureset is more opimimum when you're looking at it from an EE side; better output per area utilized. I'm guessing you're just mad that the PSP SIMD has more functionality built in? :)

And PCEngine doesn't stop talking, huh?
 
Vince said:
I would assume that th present featureset is more opimimum when you're looking at it from an EE side; better output per area utilized. I'm guessing you're just mad that the PSP SIMD has more functionality built in? :)

And PCEngine doesn't stop talking, huh?
Mostly Faf is upset about SPE's changing from a more natural way of thinking vectors (especially for 3D graphics, but you do not have to call the register fields x, y, z and w you can still think them as r, g, b and a) to a surely more hardware efficient and surely more generic, but more "unnatural" way of thinking about vectors. It is the AoS vs SoA argument.

In reality both him and others probably already have their VU1 code ALREADY using vectors in SoA form as it is faster on VU's too, but what you would lack from SPE's (a bit less from VMX-128 maybe, didn't they broadcast and other horizontal math operations or only dot-product's ?) are horizontal operations such as broadcast (single field used as operand with multiple fields of another register) or operations such as swizzling which are replaced by the less natural permute operations.

Also, SPE wise... until GCC improoves enough and/or XLC is available as middleware for PLAYSTATION 3 development loading and storing unaligned scalars will be a problem (even with XLC loading scalars will either require you to waste a QW in LS or manage to pack and keep track of scalars in QW when they get in the LS):

Re: About SPU's load/store method
Originally posted: 2005 Aug 30 12:56 PM
Barry_Minor
Post new reply

The instruction sequence for a scalar load on the SPE is:


lqd $5, 0($2)
rotqby $2, $5, $2



where $2 starts with the EA of the word you want to load into the preferred slot and ends with the scalar in the preferred slot.

The code sequence for a non-quadword aligned scalar store is:


cwd $2, 0($5)
lqd $6, 0($5)
shufb $2, $3, $6, $2
stqb $2, 0($5)



where :
$3 = scalar to store, located in preferred slot of the register
$5 = EA of the target scalar in memory
$6 = quadword containing the scalar in memory

Of course the compiler generates these sequences and schedules them for you so as a C/C++ programmer you are unaware of all this stuff.

Of course it does not help when processors like ALLEGREX contain a quite nice SIMD ISA that puts you in control of how the register set is viewed and provides tons of specific instructions. It is also nicely splitting scalar code and vector code between the scalar FPU and the VFPU.

Who knows what would have been like with 3-4x R12000i CPU's clocked at 2-2-5 GHz with a scalar FPU+VFPU combo... maybe it would have been possible, maybe not... but you can dream sometimes :).
 
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Cell seems like the achilles heel of PS3.

In terms of cost and developer dislike.

And it's the main part Sony designed..
 
I pity the people that spend all day making up false information (mostly Xbox fans in my experience) to spread FUD on forums.
 
Bill said:
Cell seems like the achilles heel of PS3.

In terms of cost and developer dislike.

And it's the main part Sony designed..
however hard you try to bend reality ,you' ll just achieve to bend yourself..
 
Well dont worry, Sony's still probably going to win, thanks to Nvidia.

Something like the Xcpu, unified memory, and the RSX would be better though.

They could launch that cheaper and faster, and arguably more capable.

I love everything about the X360 design, except the EDRAM. That's a big "except".

But I guess Cell adds to PS3's "high tech, uber powerful" mystery.

We will see if it plays out..
 
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xbdestroya said:
What the hell PC-E, your post came *after* his! And no wonder why, as here's his full post:

Link

Good god man, talk about selective screening to 'prove' a point.

Plus the whole 'why would they need IBM thing' is explained at the beginning of that thread as well: Sony simply wanted to bring them on for their expertise, not over some sort of inherent roadblock on 'main core, sub-core' implementation.

It was *after* this post of mine.

So the original plan was a CELL with only SPEs?

Basically ONE said Toshiba's idea was having them all be SPEs with one of them being a master. He also said the other option was not having a master SPE at all. ;)

SedentaryJourney said:
I know! Anyone with absolutely no engineering talent whatsoever could totally do that in like 3...maybe 7 seconds man!

Who said anything about Toshiba not knowing how to design ICs? You've completely missed the point. Taking a licensed MIPS core and tacking on VUs and making it work isn't rocket science. Heck even SEGA's engineering department could take a CPU and tack on a coprocessor.

The_Standard said:
PC-Engine:

You have no idea what you are talking about. The twin "ring" EIB design, the very backbone of the Cell, came from KK-san's own head.

Yeah right without a microprocessor design degree? I think the only thing KK contributed was: "Oh please please I want it to look symmetrical. Oh please I want Power of 2. Oh please I want asthetics."
 
PC-Engine said:
Yeah right without a microprocessor design degree? I think the only thing KK contributed was: "Oh please please I want it to look symmetrical. Oh please I want Power of 2. Oh please I want asthetics."

Yes, I forgot he got a BA in Art History and spent his time since he got into Sony drawing their ads...
 
blakjedi said:
Faf - Im interested in learning more. How are SIMDs a step backward?
Feature wise, they are a lot more primitive then what we got to work with in the past. Yes there's a lot more of them, but I am not complaining about raw performance here.
And I was pretty much referring to both chips here, and quite possibly Revolution as well.

Mefisutoferesu said:
What exactl do you mean by "real man's" SIMD?
It's a name Deano jokingly gave to vertical-only SIMD. I guess complaining about it would make me a bit girly ;)
Anyway Pana worded some of what I referred to, and I already ranted long in this post so let that be enough for now.

Panajev said:
It is the AoS vs SoA argument.
I am not rigidly stuck on one notation over another - I just don't like it when an ISA forces me to evaluate math in every algorithm as a special case unto itself (if I want efficiency that is).
Anyway here's a fun mental excercise - try giving some thought what it would take to make your atomic element a 4x4quad instead of 4x1 vector in your entire codebase (all of it, not just vector/matrix arrays).
I'm not even gonna ask you to figure out what a good class interface would be for such a type, just consider the data layout implications alone.

ERP said:
Personally I thought the VU implementation was already a step backwards from the Dreamcasts SH4 SIMD......
I don't quite agree with that.
It's true SH4 had nice mapping of register pool as floats, vectors, and matrices, which is just about as flexible as you can get for data access in registers.
But on the flipside, the FPU register pool was quite tiny and the ISA was very barebones - DOT instruction is nice and all, but it doesn't make a powerful SIMD by itself.
VUs just made a whole lot of things easier IMO.

That said, we've had bigger and better things then either since then, but I'm not going there now :p

Vince said:
I would assume that th present featureset is more opimimum when you're looking at it from an EE side; better output per area utilized.
Oh I never said I don't understand their reasoning - but that doesn't make me like it any better, knowing something has good output/area ratio don't make writting code for me any easier.
...and yea that other thing too...
 
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london-boy said:
Yeah he was the electrician.

He came a long way you must admit.

He came a long way but not in terms of designing a microprocessor. He basically took the SNES CD idea and turned it into a Playstation. He didn't design any of the chips nor does he know how. He probably could've designed some of the analog parts of the Playstation though.
 
PC-Engine said:
No he got into SONY by working with analog circuitry. ;)
And you'd have us believe that it's impossible for someone to be good at something without a formal education or Degree Certificate? KK can't know anything about digital electronics because he was trained in analgoue circuitry and no-one learns anything outside of school, so there's no way KK could learn about processors as the industry developed. What the hell was he doing working on LCD screen technology at Sony for when he has no education on the matter? Without a degree in LCD technologies obtained in 1975 when he graduated Ken obviously couldn't contribute anything to the technology.
 
Shifty Geezer said:
And you'd have us believe that it's impossible for someone to be good at something without a formal education or Degree Certificate? KK can't know anything about digital electronics because he was trained in analgoue circuitry and no-one learns anything outside of school, so there's no way KK could learn about processors as the industry developed. What the hell was he doing working on LCD screen technology at Sony for when he has no education on the matter? Without a degree in LCD technologies obtained in 1975 when he graduated Ken obviously couldn't contribute anything to the technology.

What did he contribute to LCD technology? What part of a microprocesssor has he designed? There is theory then there is practice.
 
PS3 is teh DooMED and Kutaraggi can only wield a soldering iron but he can not use l33t soldering skillz to make a CEll !!!! :LOL:
 
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