The new chips are expected to run at 1.2 V or less,[24][25] versus the 1.5 V of DDR3 chips, and have in excess of 2 billion data transfers per second. They are expected to be introduced at clock speeds of 2133 MHz, estimated to rise to a potential 4266 MHz [1] and lowered voltage of 1.05 V [26] by 2013. DDR4 is likely to be initially commercialized using 32 – 36 nm processes,[1] and according to a roadmap by PC Watch (Japan) and comments by Samsung, as 4 Gbit chips.[23][19] Increased memory density was also anticipated, possibly using TSV ("through-silicon via") or other 3D stacking processes.[3][1][2][27] The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC.[27] X-bit Labs commented that "as a result DDR4 memory chips with very high density will become relatively inexpensive".[1] Prefetch will also potential increase up to 16 bits per clock, compared to DDR3's 8 bits per clock.[3]
DDR4 also anticipates a change in topology. It discards dual and triple channel approaches (used since the original first generation DDR[28]) in favor of point-to-point where each channel in the memory controller is connected to a single module.[2][3] This mirrors the trend also seen in the earlier transition from PCI to PCI Express, where parallelism was moved from the interface to the controller,[3] and is likely to simplify timing in modern high-speed data buses.[3] Switched memory banks are also an anticipated option for servers.[2][3]
