anexanhume
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It's a shame all these memory manufacturers all keep having mishaps. Fortunately, they only seem to occur when the market is oversupplied, so it just has the effect of raising prices.
Next Generation Hardware Speculation with a Technical Spin [post E3 2019, pre GDC 2020] [XBSX, PS5]
- Thread starter DavidGraham
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- john sell
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I can wait 13 minutes for the prices to rebound.
Unfortunately that's not how it works.
https://www.techpowerup.com/256909/...outage-6-exabytes-of-nand-production-affected
Return to standard manufacturing rates is expected to only occur by mid-July.
Damage includes impacted wafers that were being processed, the facilities, and production equipment, hence the need for an extended inoperability period to seriously assess damages and required reinvestment. 35% of the world's NAND supply is produced at this Yokkaichi Operation campus (which includes six factories and an R6D center), so this outage and NAND flash loss is likely to impact the global markets.
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This isn't going to impact anybody who has a contract for NAND production for mass market products, this will merely limit the amount of NAND available outside contracted bulk production which will likely drive up consumer prices a little for a few months if stock becomes low.
D
Deleted member 91098
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According to a user on /r/amd there was a TSMC meeting last week were the following info graphic was taken: https://pc.watch.impress.co.jp/img/pcw/docs/1193/327/46_o.jpg
I wonder what they categorize as "Large Die". 300 mm² and more or like what is likely for monolithic console chips, or ridiculous dies like Knights Landing (682 mm²) and Nvidia TU102 (754 mm²)?
HVM of 7nm kicked off during April 2018 for TSMC so the graph for large die refers to a Q3 2018-Q1 2019 timeline. You wouldn’t expect a next gen chip to be in high volume production during that time.
That’s probably Vega or something else.
gamervivek
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anexanhume
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Navi and Vega 7nm are probably their highest volume examples.
ronvalencia
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AbsoluteBeginner
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Who cares what would it be early dev kit? We know at beginning of a year there was no Navi, and we know Navi has palpable perf/tflop advantage therefore they had to put some big Vega inside dev kits to emulate Navi itself.
Here are my theoretical performance estimates based on 7nm DUV & EUV designs
On 7nm DUV (9-10TF conservative estimate)
60CUs total - 54CU enabled - 320 bit bus - 3 Shader Engines -> 404mm2
But following design rules that prioritize density over frequently (empty spaces on 5700 die shots), should bring it closer to 390mm2 then shrink to 331mm2 when 6nm becomes available 2021-2022
Die Size estimates based on LiabeBrave graphic and @Proelite comments
66CUs total - 60CU enabled - 384bit bus - 3 Shader Engines -> 348.68mm2 (335mm2 with a 320 bit bus)
On 7nm DUV (9-10TF conservative estimate)
60CUs total - 54CU enabled - 320 bit bus - 3 Shader Engines -> 404mm2
But following design rules that prioritize density over frequently (empty spaces on 5700 die shots), should bring it closer to 390mm2 then shrink to 331mm2 when 6nm becomes available 2021-2022
Die Size estimates based on LiabeBrave graphic and @Proelite comments
75mm for CPU
81.6mm2 for 320 bit bus (20GB)
69.99mm2 for 3SEs (ROPs, cache, etc.)
IO 20.72mm2
10.85mm2 GPU CC (CP, ACEs etc.)
146.7mm2 30DCUs with RT (60CUs)
Total:
404.86mm2
81.6mm2 for 320 bit bus (20GB)
69.99mm2 for 3SEs (ROPs, cache, etc.)
IO 20.72mm2
10.85mm2 GPU CC (CP, ACEs etc.)
146.7mm2 30DCUs with RT (60CUs)
Total:
404.86mm2
- 54CUs @ 1400Mhz = 9.67TF (lowball)
- 54CUs @ 1500Mhz = 10.36TF (very likely)
- 54CUs @ 1550Mhz = 10.7TF
- 54CUs @ 1592Mhz = 11TF (best case scenario)
66CUs total - 60CU enabled - 384bit bus - 3 Shader Engines -> 348.68mm2 (335mm2 with a 320 bit bus)
75mm for CPU
97.92mm2 for 384 bit bus (24GB)
69.99mm2 for 3SEs (ROPs, cache, etc.)
IO 20.72mm2
10.85mm2 GPU CC (CP, ACEs etc.)
161.37mm2 33DCUs with RT (66CUs)
Total:
435.85mm2 7nm DUV
348.68mm2 7nm EUV
97.92mm2 for 384 bit bus (24GB)
69.99mm2 for 3SEs (ROPs, cache, etc.)
IO 20.72mm2
10.85mm2 GPU CC (CP, ACEs etc.)
161.37mm2 33DCUs with RT (66CUs)
Total:
435.85mm2 7nm DUV
348.68mm2 7nm EUV
- 60CUs @ 1500Mhz = 11.5TF
- 60CUs @ 1600Mhz = 12.28TF
- 60CUs @ 1693Mhz = 13TF
Why only 20.72 for IO and not 37.72 ?
And I found 1.25 for density gains of EUV on your 66CUs APU. 435.85 / 348.68 = 1.25
The 7nm EUV size of your 66 CUs APU should be around 363.21 mm²
I think the number of significant digits in these calculations would merit a teacher comment if presented on a test.
snc
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Why 18 multiplier is important ?
Metal_Spirit
Regular
Why 3 Shader Engines?
GCN had a limit of 16 CU per Shader Engine, with 4 shader Engines used for 64 CUs.
RDNA is using 10 Double CUs per shader Engine. Or the equivalent to 20 GCN CU per SE.
As we can see, the 16 limit is beated if we compare CU, but not if we compare GCN CU with RDNA Double CU.
IF RDNA simply created a new CU that is a Double GCN CU, that would mean we can have 16 Double CU per Shader Engine, or 32 GCN CU per Shader Engine. In that case, 2 shader Engines would have 64 GCN CU, allowing RDNA no reach 128 GCN CUs keeping the same efficiency as GCN on 64 CU.
And in this case you would only need to disable 2 Double CU, or 4 GCN CU. This would allow 56 CU.
At 1800 Mhz, this would go to 12.9 Tflops.
You mean 60 activated CU ? 64 - 4 ?
I think 3 SE won't be possible with RDNA because of the butterfly structure. It's either 2 or 4.
snc
Veteran
That would be rather silly argument
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