Which areas of the footprint of the GPU and HBM stacks in a Vega 7 MCM are you considering to be the memory controllers?
The PHY of a GDDR6 was described in a video earlier in the thread to be 1.5-1.75x bigger for HBM2 of the same bandwidth.
The 256-bit subsystem of Navi takes up ~3/4 of two long sides of the die, while a roughly equivalent two stacks of Vega 7 take up one side, with a gap between them that may or may not be entirely controller-related.
I haven't seen a clear description of which blocks would be the actual memory controller logic, or if Vega's higher-end features and HBCC would exist in similar form for Navi.