Current Generation Hardware Speculation with a Technical Spin [post launch 2021] [XBSX, PS5]
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The APU reduces the amount of L3, which is a common sacrifice for mobile.
The cores are architecturally the same, to my knowledge.
Barring some Sony-specific reasoning, cutting the FPU doesn't have any clear justification. The laptop chips are not performance consistent, they aren't in a super-constrained power range, and it's a tweak of the DVFS to adjust the ceiling if need be.
I'm still not confident that what Sony did was really necessary, given the number of other adjustments that can be made without potentially paying for a revised CPU that loses capabilities rather than gains them.
There aren't that many benchmarks of games using avx vs sse you can find, but here's one. This is on an 8700k. The difference in current games is small or negligible.
SSE vs AVX how much performance different ? Grid 2 and Project Cars 2 1080p low test - YouTube
SSE vs AVX how much performance different ? Grid 2 and Project Cars 2 1080p low test - YouTube
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I'm not sure that provides a comparable scenario to what the benchmarking for the 4700S showed, which makes a Zen2 vs PS5 that has the SSE cut in half as well.
Kugai Calo
Regular
Wait what?
If that's the case, it means that the IPC of floating point instructions on PS5's SoC in general is lower than a standard Zen 2, not just AVX256 instructions. (Not necessarily half the IPC, since some code don't exhibit much inherent ILP, but lower)
A reminder that since AMD64, SSE is floating point, since x87 is deprecated.
Wait, does that mean PS5's CPU core has the same theoretical floating point IPC as PS4's Jaguar cores? Back when Series X was announced they talked about the CPU being 4x faster than Xbox One. 2x the IPC and 2x the clocks. Obviously real performance would be better on PS5 vs PS4 because the clocks are higher, but still.
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no game we've seen released on console has switched to AVX yet. It may or may not ever happen this generation.
And wrt the FP performance, it's probably negligible unless benchmarking 120fps performance for a lot of titles. A real bottleneck would have cropped up by now I think if it's an issue at 60fps or below.
Not many next-gen/new features are being really extensively used as of yet, be it advanced cpu features or things like fast SSD, RT, mesh shaders, vrs etc etc. The start of this generation where most if not all cross platform games are cross-generation we have a hard time concluding each systems true capabilities.
Furthermore, the ps5 cpu might be weaker than zen2 cpus, its however a very healthy increase over the tablet jaguar cpus that never should have happened.
Most games can exceed 60fps on a 3+ghz 8 core Bulldozer, and they wouldn't have been as well optimized as the console releases. Also, just because they have the same theoretical peak performance doesn't mean that the Zen2 FPU isn't more efficient in practice. So, I don't know if it's bore out in games yet.
In 2013 at the price point and power budget both consoles needed to hit it would have been an 8 core Jaguar or a quad core Atom (without hyperthreading) or a dual core i3. Also, I'm unaware of any tablet running a Jaguar CPU with more than 2 cores or more than 1ghz. They never even made 8 core laptop APUs. If the enhanced consoles have proven anything, it's that most games of their generation are still held back by the GPU.
Kugai Calo
Regular
I believe the average fp IPC would still be higher, but at peak, yes
Kugai Calo
Regular
I think you’re getting the wrong picture. Sony didn’t remove any feature from their CPU, instead they reduced the performance. So the CPU will be able to execute AVX256 instructions just like any other Zen 2 out there, but if a standard Zen 2 can retire 4 SSE instructions or 2 AVX256 instructions per cycle, PS5’s CPU can retire 2 SSE instructions or 1 AVX256 instruction per cycle.
Could it possibly be related to hardware level backwards compatibility? Something related to vector instructions per cycle?
It would seem really odd, but could there be some part of PS4's software ecosystem that would break if certain performance limitations were exceeded?
The changes aren't to increase performance, or to significantly reduce footprint, and if they aren't about power management, could they be about something fundamental to how the PS5 must operate?
I'm pretty sure SSE has been useful for games for many years now. There are lots of Vector3 and Vector4 operations that you do on the CPU even for relatively simple 3D games, especially if you use physics. Unreal offers you types that use various vector optimisations in the background, so bums like me don't have to bother remembering maths from 20 years ago, or learn intrinsics.
SSE has been used in games for the past 20 or so years but ok. Anyway, it was either the cut down SSE/AVX performance or much lower clocks and Sony probably made the right decision to go with 3.5ghz max clock instead of not even 3ghz when AVX/SSE are steaming at max usage.
My current working hypothesis is that it's about power too, but 3dilettante seems to think that power management could have been addressed with a less invasive and significant redesign / tweak. And SSE should be rather less demanding in terms of peak power, so why does that see similar cuts to 256-bit AVX?.
I'm just thinking that perhaps there could be something more fundamental to how PS5 is forced to operate going on.
Oh there most certainly is, power management was probably one of the factors for their CPU design decisions. Hardware BC could be one another reason. The whole console is probably designed with the same philosophy in mind. Take the 36CU part for example (and other GPU design decisions), i cant think of any other reason then BC as the reason for going narrow/fast which decreases efficiency aswell as performance. Sony is more on the hardware side of things for BC whilest MS isnt as restricted there using their software side of things instead.
MS having the better-specced hardware, Sony has the huge advantage of API's, more popular console and a head start in exclusives that use the next gen features more prominently.
The mix tested points to a noticeable drop in peak IPC. There could be mixture-dependent differences, since it's not clear that the tests shown indicate if there's more or less contention with non-arithmetic ops things like moves and shuffles.
The non-descript fpu mix tests might show that there's some leeway in mixes that aren't purely one operation.
Some of the CPU-limited frame times we've seen where people chalked a minor deficit for the PS5 might have been worsened by this. Since the clock speed shouldn't be an ideal linear scaling, perhaps the results where it seemed like there was such scaling are evidence of FPU contribution.
Another area is where the PS5 doesn't always show a lead over other current gen consoles in load times, proportional to the SSD's bandwidth advantage. Since games often do other work in that portion, perhaps some of that lost performance advantage is related.
I feel like this isn't helpful given that the comparison is between two OoO superscalar processors, so what ports get hit in what cycle is already variable. Since the PS5 is generally not down-clocking to equivalent speeds, the raw performance aspect doesn't seem to be an issue presently.
A particularly stringent power ceiling, or a quirk to AMD's DVFS that somehow didn't give Sony what it wanted could be at issue. I don't know if Sony got anything else tweaked or added when this was done to the FPU.
For laptop chips, AMD doesn't care enough about consistency to do more than tweak firmware.
Perhaps Sony was afraid of backwards compatibility issues before having hardware, and then found out later that they wasted time hobbling the FPU?
It does seem like Sony's BC patents indicate a level of paranoia about consistency that has been mostly discarded, so living with a mistake isn't necessarily out of the question.
Another bit of precedent is that Sony has made custom tweaks that seem to have not made much of an impact or wound up not being of much use, and this could be another.
davis.anthony
Veteran
Could it be that in order to get the I/O complex on die and still remain within transistor and power budget they had to make some cuts to the FPU and other changes they thought were small?
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