AMD: R8xx Speculation
- Thread starter Shtal
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CJ: Hah, well that's different then - cheers! I've got to admit that in such a line-up though, I've got a lot more difficulty believing RV740 has a place in the 55nm era. Hmm, 40nm shrink of RV770 with 128-bit GDDR5 and no sideport maybe? 
One interesting dynamic to take into consideration is that the extra cost of GDDR5 is only partially per Mbit; so while a 512Mbit GDDR5 chip will be X% more expensive to manufacture than a 512Mbit GDDR3 chip, when both are 1024MBit the GDDR5 would only be Y% more expensive, where Y<X but Y>X/2; the same dynamic applies to DDR3, fwiw. The magnitude of this difference is hard to quantify without being a real insider though, especially with GDDR5 which understandably generates less interest from the likes of Semiconductor Insights. This is semi-OT, but I thought it'd be a good moment to point it out given my above speculation.
One interesting dynamic to take into consideration is that the extra cost of GDDR5 is only partially per Mbit; so while a 512Mbit GDDR5 chip will be X% more expensive to manufacture than a 512Mbit GDDR3 chip, when both are 1024MBit the GDDR5 would only be Y% more expensive, where Y<X but Y>X/2; the same dynamic applies to DDR3, fwiw. The magnitude of this difference is hard to quantify without being a real insider though, especially with GDDR5 which understandably generates less interest from the likes of Semiconductor Insights. This is semi-OT, but I thought it'd be a good moment to point it out given my above speculation.
=>Arun: Interesting. It could mean that RV730 or any other 128bit GPU could get 512 MB of fast GDDR5 memory, but it seems RV730 will be stuck with GDDR3. And when new chips come out, the situation on the market could as well be very different from how it is now - the demand for GDDR5 will grow and I don't believe that the other makers would gladly leave the whole market to Qimonda.
=>Wirmish: I've been thinking about a similar concept a year ago or so, although not theorizing it to such extent as you did. It would appear you have solved the master-slave bandwidth problem, but you have not solved the second problem and created the third.
- Where do you put the memory controller? Onto the master chip, which is the only one with RBEs? But then the master chip's RBE and memory controller would have to be designed with the slaves in mind, otherwise this would be the bottleneck. And if the master GPU was to be used in single configurations, some parts of the chip would stay unused. Which is not ideal, considering that this master-slave approach should primarily solve the problem of having unused parts of the chips.
- It would need some serious work on the software to make it run. What you're proposing is generally an asynchronous multi-GPU system.
=>Wirmish: I've been thinking about a similar concept a year ago or so, although not theorizing it to such extent as you did. It would appear you have solved the master-slave bandwidth problem, but you have not solved the second problem and created the third.
- Where do you put the memory controller? Onto the master chip, which is the only one with RBEs? But then the master chip's RBE and memory controller would have to be designed with the slaves in mind, otherwise this would be the bottleneck. And if the master GPU was to be used in single configurations, some parts of the chip would stay unused. Which is not ideal, considering that this master-slave approach should primarily solve the problem of having unused parts of the chips.
- It would need some serious work on the software to make it run. What you're proposing is generally an asynchronous multi-GPU system.
Yes, remember there is a die size penalty to supporting GDDR5 too. I/O isn't free; somehow, everyone wildly fantasizing about many-chip solutions seems to be missing that too...
The part that's even worse is that it doesn't always scale very well with process nodes: just look at the I/O part of CELL from 90nm to 65nm and 45nm...Hmm? Samsung and Hynix are both very much in the game; in fact, Hynix seems to be slightly ahead for 1024Mbit/2048Mbit chips!
No RV870 in first quarter of 2009!
Why partially for ATI ??
http://forums.vr-zone.com/showthread.php?t=332303
Why partially for ATI ??
What's a partially serious issue, anyway?
What I meant partially is both Nvidia and ATI has 55nm chips, why would it effect Nvidia more going to 40nm then ATI - or because ATI has better experience jumping to smaller process.
=>Shtal: It's not the act of going to 40nm that is supposed to affect nVidia. The delay of 40nm availability is. Right now, ATI beats nVidia in perf/mm2 with RV770 and RV730. nVidia planned to catch on by rushing to 40nm, but since they can't do that, their schedules are affected. ATI probably also had some schedules, but chances are if they miss it, noone will notice. Remeber the G200 was six months late and nobody noticed.
Prometheus
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Wont it be easier for ATI to move to 40nm since their chips are quite smaller than Nvidias monster chips?
"Monster chips" are not an issue here - G200 isn't the only chip nVidia makes, you know. And if 40nm is not suitable for monster chips, they can always make a GX2. Right now, the biggest problem 40nm has is it won't be available until Q2'09, which means we won't see any 40nm GPUs before Q3.
TSMC's 40nm is 45nm halfnode or something along those lines, I think?
Wouldn't be so sure about that. Few days ago TSMC shed some light on their 32nm and 28nm processes and the full-node/half-node approach is, let's say, not what it used to be.
Here it is: http://www.eetimes.com/rss/showArticle.jhtml?articleID=210604347&cid=RSSfeed_eetimes_newsRSS
http://www.digitimes.com/news/a20080930PR201.html
Here it is: http://www.eetimes.com/rss/showArticle.jhtml?articleID=210604347&cid=RSSfeed_eetimes_newsRSS
http://www.digitimes.com/news/a20080930PR201.html
How about 45nm? let say Q1-2009.
Intel already produce core2 based on 45nm
TSMC canned 45, but it's a bit of a misnomer anyway. Feature size is somewhat variable, especially when doing lithography at these levels.
according to this source Rv870 will feature 1GB GDDR5 on all standard models
good news I guess
http://news.ati-forum.de/index.php/en/news/34-amdati-grafikkarten/74-rv870-1gb-gddr5-standard
good news I guess
http://news.ati-forum.de/index.php/en/news/34-amdati-grafikkarten/74-rv870-1gb-gddr5-standard
Does that mean for R8xx GPUs AMD intends to utilize simplified PCBs on all models and use GDDR5 instead? So they could possibly intend to reduce costs and potentially use 64/128/196 bit busses for all their low end and mainstream GPU offerings?
It makes sense to me at least, because IIRC PCB costs are actually a reasonable percentage of the total cost of your standard graphics card. So smaller buses but faster memory could be the order of the day?
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