AMD: R8xx Speculation

If this is correct than it's pretty much in line with the 1/3 rule (1/3 to programmable cores, 1/3 to fixed function and 1/3 to all the rest)

 

Well I suspect there's more stuff (related to threading and import/export for the cores) outside of that area, but there's no decent way to say how much. Can't even say how much more there is for RV770.

 

I see a central (global data share?) section, 7 columns and 11 (!!) rows of square blocks. Comparing those things to corresponding architecture schemes, I think it could very well be identified like this:



So ... does Cypress actually have 5*16*11*2 = 1760 shaders?

It's a pity that that lower part isn't fully discernable - but it really seems like 11 rows if you look closely ...

 

I'm not saying your representation of the die is neither correct or incorrect, but please don't forget, that diagram of RV770 didn't reflect actual layout of the GPU.

 

Pretty interesting interpretation.

Bear in mind that each of the four squares that appear to be the ALU sections of a core includes 64KB of register file. So the amount of space taken by LDS (32KB + atomics logic + read request queue + output queue) shouldn't be anywhere near as large - say 1/3 at most? And TMU L1 is tiny, too.

As for 11 cores per shader engine. Well, I wouldn't rule it out, frankly.

The central area is unlikely to be GDS - it's only 32KB. It could actually be nothing more than the TMUs or local scheduling or it could be stuff which in RV770 was outside of the central region.

I can't think of anything much that can be concluded.

 

I know. It's funny how well the diagram actually seems to fit the discernable geometry, though.

Why hasn't anyone actually done a real die shot of RV870 until now? I mean - that picture was drawn from a video a guy filmed while dissecting his HD 5870 card with a knife! Surely some more "professional" journalists could do a lot better than this given some technical support and better equipment?

It would make a great news story

 

I would.

 

Now that the cat is pretty much out of the bag, can you tell us why you never released a die shot of Cypress?

 

He obviously means that there are actually 12 of them.

 

There was some speculation about RV770 and 840SPs or so... Same here, eleven cores are more likely than more SPs per SIMD tought.

 

What level does it make sense to plan redundancy? Inside a SIMD, at Thread Processor level? Bigger? Whole SIMD? Smaller, per SP? Depends on if a SIMD requires all 80 SP's to be adjacent or if they can be distributed; whats the commonality of a SIMD design.

 

Looking at the picture, I really don't think so.

I seriously thought I could make out an 11th row down there where the picture started to get a bit fuzzy (especially looking closely at that middle part and how it seemed to run on straight beneath what I thought to be row #10) - but 12 rows? No chance. It wouldn't make a lot of sense to have that much redundancy either.

Nah, I think he actually meant it's just 10 rows - which, on consideration, seems rather logical given that there should still be a lot of stuff beneath that 10th row (comand processor, the entire graphics engine, the dispatch processor, some more cache stuff - you name it. That's assuming all the ROP stuff is actually located at the upper part of no-X's tweaked picture ...).

I just wished we had a better quality shot at hands.

 

17x VLIW-5 per SIMD seems probable from the RV770 die shot, which appears to tally with various patent documents for redundancy which have one extra per 16. Equals 850 total.

 

64KB.

 

Whoops