As above post, it's how people were discussing. Posting 'this website confirms/denies the rumour' and 'everyone's stupid for believing/denying the possibility' isn't technical discussion, and I had removed a page of that sort of talk.
Xbox One (Durango) Technical hardware investigation
- Thread starter Love_In_Rio
- Start date
- Status
LightHeaven
Regular
That efficiency thing is because each of Xenos processors can do more instructions per cycle than what the majority of the code needs, and the extra power is all but wasted because it can't be used for other instructions. On some earlier Gamefest presentation Ms rated Xenos as a 140ish gflops part, compared to that, a 1.2tflop gpu with all that actually accessible for the code, would indeed offer 8 times the raw flops performance.
Betanumerical
Veteran
They are probably talking about more real worldly FLOPs by taking into account efficiency because the XBOX 360 is VLIW5(4?) and the XBONE is Scalar..
If we are interesting in comparing Xbox One efficiency relative to Xbox 360 perhaps we could restate what you said like this:
Factor 1: Call it F1 = (1/0.5) and it is due the efficiency in certain codes as you said.
Now I am wondering what some of the other factors might be.
For example, perhaps Xbox One Efficiency relative to 360 is not just F1 but perhaps F1 * F2, etc.
For example, for texturing do we get a substantial F2 from PRT, ESRAM and compression (move engines) all working together?
So do we end up with a relative efficiency more like F1 * F2?
And then we also get more work done from more Clocks & ALU's?
So "work done" might be expressed (relative to 360) as something like:
F1*F2*[(Clock X1)/(Clock 360)]*[(ALU X1)/(ALU360)]
???
Just wondering. Could some of the GPU experts comment? Am I making any sense?
I am not trying to talk about flops. I am trying to talk in terms of what the GPU can actually render in a give time. And I am curious how big F2 (architectural related efficiency improvements) might be after 8 years from Xenos to Xbox One. Possible quite big?
Second question for the GPU experts. Since this release date is about 2 years from the Tahiti/CGN release date (Jan 2012 versus Nov/Dec 2013) should we be expecting CGN or CGN 2 or CGN 2.5 or CGN 1.5?
COPS N RAPPERS
Regular
No, I was showing two separate sources that did have some accuracy and shedding light to the speculation. and i'm aware of the stir that was caused and it was not intended.
It's possible that the original source that neogaf posted had correct information BUT mistaken the PCs that were in ready to run Xb1 games as an official spec change. On the Other hand one would say the GPU and clock speeds of the XB1 were left out of official information; which might have given leeway for them to assemble unorthodox devkits.
----------------------------------------
Now for a complete architectural change to happen it might involve them breaking protocol on a lot of what they said unless either their figures shown were loose, or they've already conducted changes in separate display models. The idea alone of them doubling on memory does alter the information that was projected.
Xbox 360 is Vec4+Scalar, not VLIW5 (nor 4)
All the multipliers in those docs refer to "real world" improvements, thus the little *. The 360 had a 5 wide vector in the GPU. Developers used, on average, 3 of them. GCN is scalar, so utilization of the ALU should be almost 100%. The same for the CPU. An 8 core jaguar is theoretically the same FLOPS as the 360 CPU, and half the FLOPS of the Cell. But in real world usage, that jaguar can get 6 times the work done, and is therefor 6 times faster.
east of eastside
Newcomer
What is "Depth"? Does that mean Xbox One could be upgraded to 16GB but not 12GB in its existing configuration? (512x16 vs 1GBx16)
Best I can tell from the Wired photos, Micron part number (in the photos) and Micron's web page it should be possible to change to either 12GB or 16GB with no PCB change. So a minor part number change on the bill of materials.
Either two of the channels go to the 2x density chips or all four of the channels go to the 2x density chips.
So I think it is entirely possible. But in the 12GB case it would be dual channel for 4GB of the memory space and quad channel for 8GB. So you would likely want to put the Windows/Apps bit in the 4GB of dual channel. (12GB assumes the memory controller is happy with that config.)
There is another way which would require memory on the back of the board. It is entirely possible that the PCB was already designed for this. (Why? So that beta kits (not PC based, but based on final hardware) could use the exact same PCB and the only change would be to mount the additional 4GB to match the 12GB in the alpha ***PC BASED*** dev kits.)
This other way is dual modules per channel. Keep the existing modules as they are and add the same number of modules of half the density to get to 12GB. That way it is all quad channel but now you have two chips loading the channels. Not sure if the memory controller would like that at 2133 MHz.
The additional memory would likely go on the back of the board.
Edit: If they don't want to put memory on the back of the board or if it causes trace matching issues then maybe for the beta kits they can get extra memory for dev and debug capability by just using 8G modules instead of 4G modules.
Last edited by a moderator:
And an investment in a double layer PCB would be required,that would increase the cost in production just to add a few chipsets on the back of it...
Can't route such a complex board with a single layer anyway (you need 2 layers to "jump" traces). These would normally be 4-layers, so 2 sides plus a ground plane, and possibly a power plane (Or maybe not?). I'm guessing putting chips on the back only requires lots of vias, and that would be a negligible expense compared to the cost of the chips.
I would bet a board of that complexity has many more than 2 layers.
So we will be hearing about it soon I suppose.
- Status
Similar threads
