Next gen architecture is about efficiently meeting demands of future workloads not "doing more with less". Sony doesnt base console specs on consumer PC averages, it makes forward looking bets 100% based on developer needs over a 7-8 year console cycle. Respectfully what you've proposed wouldnt be smart since you cant just plug and play PNM and PIM into a memory controller. You're comparing PNM(Persistent Memory) and PIM(Processing In Memory) which are enterprise side academic technologies with no proven and viable deployment, no driver stack, no compiler runtime support in gaming consoles. Even if you managed to incorporate these systems, you still wouldnt negate the need for higher physical memory capacity and bandwidth when it comes to feeding real-time graphics pipelines and AI inference engines for next gen silicon and workloads. You'd end up increasing the latency along the memory hierarchy by incorporating such an additional layer. IIRC Xbox One base console added embedded SRAM(ESRAM) as a cache between the GPU and DRAM, with a theoretical 204GB/s of memory bandwidth. But this was a disaster in practice with developers only having about 68GB/s usable due to inconsistent performance. Sony's simpler 8GB of GDDR5(176GB/s) with higher memory bandwidth outperformed the theoretical (204GB/s) memory bandwidth on the base Xbox One without a need for OS and SDK level optimizations, and no need for extra developer work. Simple wide physical memory won out over complex theoretical workarounds. Thats the smart precedent here.
What do you mean PNM and PIM don't have proven and viable deployment? They're technologies major companies are using
right now in various AI and enterprise environments! LPDDR-PIM and HBM-PIM are available as
commercial products, they aren't theories in academic papers anymore and haven't been such in years. Yes, the industries actively buying that memory are quite niche, but they nonetheless are buying them. Commercial products of the technologies wouldn't exist, if the promises they made (such as much reduced power consumption across the memory bus) weren't proven in the first place.
It doesn't actually matter if the technologies have no implementation in current consoles, because if you look at the history of technological evolution in consoles, they've always cribbed concepts from high-performance tech in other sectors & industries anyway. Many of the concepts 5th gen consoles like PS1, Saturn and N64 implemented at a mass-market scale came from things like smaller CD-ROM adoption on PC, and 3D graphics technology from specific arcade boards and hyper-expensive SGI workstations. All of those were rather small in total scale of adoption compared to the many millions of units 5th-gen consoles would go on to sell. So the fact HBM-PIM or equivalent aren't actively in use with a game console today doesn't bar them being used in a future design whatsoever.
Also, I have to correct you somewhat; PNM is something actually implemented in at least one console on the market
today, the PS5. The entire concept of the I/O subsystem is an implementation of PNM; almost all of the data processing related to storage happens directly between the storage and system memory. The I/O subsystem has buffer caches and logic to offload almost all of this from the PS5's CPU. That is an implementation of PNM, and it's been available for the mass market since 2020.
I feel you're misunderstanding the main benefits of PNM or PIM especially; bringing up increasing memory latency, well the entire point of things like PNM and PIM is to reduce the need to transfer data across the bus to begin with! By localizing the processing, you reduce the need to keep shuffling data across the bus. Meanwhile, the latency you might introduce by having another memory in the hierarchy, isn't significant and wouldn't have a significant impact on overall performance. It would really just come down to how SIE'd decide to implement something like PNM or PIM as a buffer. Do they make it a cache or make it the whole memory pool? If it's a cache, how much do they add?
In any case, considering the strong likelihood they're using AMD's x3D vCache, there's going to be at least some type of implementation of PNM or PIM in the PS6 due to that (especially if SIE extend the usage of things like cache scrubbers to that cache).
The hw compression was present on both PS5 and Series X and was fixing bottlenecks between the disk to memory. The hw blocks decompressed data between the SSD and RAM and not during active execution in the unified physical memory pool. Once you have the data resident in memory the decompression is done. So you have full uncompressed high resolution textures, AI states, BVH structures, etc. Improving compression ratios will not compensate for physical memory shortfalls if anything it only necessitates higher physical memory to take advantage of better compression ratios. On top of that you still have a need for higher memory bandwidth for Real Time RayTracing like Path tracing, virtualized simulations, ML hw accelerated upscalers like PSSR. And this is just the baseline for flagship AAA titles for a system supposed to run from 2028-2035/6. There's just no way around doubling RAM and memory bandwidth.
Well let's just be realistic here then; what's the actual chance a PS6 in 2028 can both double its current memory capacity AND significantly boost the amount of total bandwidth? Al while trying to strike a reasonable price (IMO, anything more than $599 is probably very egregious for a mass-market traditional console)? It sounds like you're expecting a doubling on both fronts but that in addition to a competent CPU & GPU to leverage it is going to push prices unrealistically high IMO.
Especially considering, SIE don't want to lose too much money on each system sold (if any at all).
Again you're looking at the improvements to disk throughput while I was talking about the memory requirements not disk. Yes Cerny with Kraken and Oodle and Andrew Goossen at MS with BCPack were right to prioritize I/O throughput. That was the biggest bottleneck moving from 8th to 9th gen. Now its back to memory and compute. ML upscaling, BVH traversal for Path Tracing are both computational and memory intensive. If Sony includes larger silicon blocks for these hw accelerators on top of hw acceration for traditional Rasterization without at least doubling of memory and memory bandwidth, then they'll have underutilized silicon. And as I mentioned earlier that wouldnt be smart engineering but very similar to the Xbox One ESRAM bottleneck but actually worse in this case. For the kind of hw they plan on creating, physical memory doubling is a necessity.
I mean it's interesting you are acknowledging on one hand the next bottlenecks being memory and compute, while also acknowledging that compute is going to require custom integrated silicon dedicated to that task, yet you're against the idea of PNM or PIM (essentially), even focusing on main memory & bandwidth of such over the cache.
IMO it's always better to try coupling & optimizing data processing as close to the compute as possible, and that means coupling the memory as close to the compute as able. Registers, caches...they're both effectively implementations of PNM or PIM. There's a decent possibility SIE treat some 32-64 MB block of x3D v-Cache like the eDRAM the PS2 had, or maybe they pair that up with some other memory in a similar role. Either way, if they're using some v-Cache, I'd 100% expect some form of cache scrubbers alongside other processing elements within the memory itself, so that's still a PIM implementation for the next console.
How much control
programmers would directly have over it, is another question.
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