No idea. But wishful thinking, if the shrink is modified to be used on a 2.5D interposer, would that solve the issue of pad area? The vias don't need much space nor much power. Not an off-the-shelf part anymore, but not nearly a complete redesign.How close is the current chip to being pad limited?
Ah oups Still there a bit of wiggle room, A2 has a max of 2.3Ghz, 45nm, 65W for the 16 cores version.The clock scaling from a 45nm part to 32nm with the same design has turned out to be in the tens of percent, not more than doubling.
If a chip is going to go for 4GHz, it is going to be designed for it and would probably get close to that speed at 45nm.
How about waiting for 20nm and have twice the cores, maybe around 200mm2? Suppose IBM have planned all along to have twice the number of cores on their next A2 chip, they have a 4-cores, a 16-cores, an 18-cores, the one in development could be 32 or 36. It still doesn't have to be a custom chip, just the next one IBM has planned for their own needs, with some modification to the memory I/O and maybe put it on an interposer.