Memory issues appear to be the biggest hurdle as well as the best opportunity to differentiate and ensure long legs. AlStrong has pointed out that it based on GDDR5 projections it is very difficult getting 2GB on a 128bit bus and very, very unlikely to see more than 2GB due to the number of dram modules needed. While I am not sold a 256bit being 'off the table" by default maybe there are some potential work arounds.
The first idea is why not a "PC-ish" design: 3 memory sticks for the CPUs and 1GB of fast GDDR5 for the GPU? Memory modules are very, very cheap. If your competitor is looking at possibly 2GB of memory, tops, due to various concerns what better way to gain an edge? 3 x 1GB sticks is very cheap and in 2012 (and looking forward into 2013-2-18) 2GB sticks may be more reasonable for supply purposes. Having dedicted CPUs buses doesn't sound like a bad idea and the potential for 6GB of system memory could be a big differentiator at a small cost. In turn, the GPU could focus on 1GB of very fast video memory. 7GB versus 2GB is a pretty big difference and when talking about streaming, open worlds, and possibly moving to alternative rendering (like voxels) this could be a game changer, even if the aggregate bandwidth is less (but enough where needed).
The other thought is With eDRAM, what is the potential for binning? Why an eDRAM for the complete framebuffer--cannot this be binned? The large cost with tiling appears to be the vertex work needs to be redone. With the setup rate not improving quickly and small polys more common Xenos style tiling doesn't appear to be the smart approach. So why not bin the buffers or have a DRAM buffer adjacent to the eDRAM?
The thought was thus: Lets say you have enough memory for a 256x256 tile (about 0.7MB). As you fill the buffer a copy is sent to a larger (and slower) cache that is able to hold your z-buffer and other various buffers. So instead of re-calculating various buffers while tiling you would essentially re-utilize what you already calculated.
This may need to take some fancy footwork, but if you wanted to utilize eDRAM this could be a way to mitigate one of the primary complaints this generation. And if such a tiling & buffer mechanism could work you could invest in a more robust eDRAM implimentation.