NVIDIA Maxwell Speculation Thread

But GK104 and GK107 GPUs already has all the virtualization features.

http://www.youtube.com/watch?v=14c6bPeCx4w

http://www.nvidia.com/object/grid-boards.html

GRID boards feature NVIDIA Kepler-based GPUs that, for the first time, allow hardware virtualization of the GPU. This means multiple users can share a single GPU, improving user density while providing true PC performance and compatibility.

GRID K1 4 x entry Kepler GPUs

GRID K2 2 x high-end Kepler GPUs

GTX 650 and above can also already stream games to clients like Shield, but not 8 clients at 1 time though.

http://www.youtube.com/watch?v=zTl-4Jr6tpA
 
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I thought something like this was possible on Quadro as well.
http://www.nvidia.com/object/sli_multi_os.html
Quoted are Fermi and GT200 based Quadros. I don't quite know why two of them are needed (with a Vt-d IOMMU on the motherboard), maybe it was to put a barrier of entry and they didn't want to do too much support..

There are other solutions such as VirtualGL on Solaris and Linux, which can be used on a regular graphics card. (any vendor, though I have to wonder about performance, overhead, latency, stability depending on what's under the hood)

The real news would be Nvidia would make the software available on consumer hardware, maybe for free. [strike]I wonder if there's a hardware encoder[/strike] there's h264 encoding right on the Kepler GPU :).

Note that the consumer Windows license bans remote use, or at best allows it as long as there's only one user. So, for the layman it would have to be linux-only.
Perhaps some CLI-only thing with no support, and a deal with Valve.. Or maybe it's for Valve only?

It's a bit weird that nvidia would give this away while they repackage it as "Geforce GRID" to sell the tech at a premium. But then again, the difference would be support (Citrix, etc.), more "enterprisy" looking hardware and the ability to use a Quadro driver.

If all Kepler and Maxwell have free-for-all multi-user for linux (and maybe FreeBSD, Solaris) I'm all for it :) hell, I've always wanted to be able to do a small LAN party with only one good computer, the rest can be old crap or thin clients.
 
I notice now that they have what appears to be several of the same structures (and others from the supposed Tegra 4 shot) pasted into the supposed shot of their i500 soft-modem as well.
2ilir9k.png

:???:
 
The bottom of the "Tegra 4" is flipped, cropped and duplicated as well. In addition to the right half of that structure being mirrored and duplicated again twice along the top. And the A15-representation from that shot seems to be in the "i500" too.
 
That explains why the "+1" core, at least the yellow part, look identical to the "4" ones. That seemed weird to me. The fifth core supposedly has a different internal organization, it should look different on a real die shot.
 
That explains why the "+1" core, at least the yellow part, look identical to the "4" ones. That seemed weird to me. The fifth core supposedly has a different internal organization, it should look different on a real die shot.

No the 5th core is exactly like the other four it is just optimized with low leakage transistors and for lower clocks.

The fifth/companion core is also a Cortex A15, but synthesized to run at lower frequencies/voltages/power. This isn't the same G in and island of LP process that was Tegra 2/3. NEW: the 5th core will run at between 700 and 800MHz depending on SKU.

http://www.anandtech.com/show/6550/...00-5th-core-is-a15-28nm-hpm-ue-category-3-lte
 
The 5th core will still look different if analyzed at a low level, but memory structures might be placed the same as with the other cores which would make it look similar with these high level die shots.
 
I seriously can't understand nV's "+1" core anymore, sure it made sense for last Tegra, but now ARM designed A7 or something as the companion core for A15's as in big.LITTLE designs, yet still nV has A15 +1
 
The 5th core will still look different if analyzed at a low level, but memory structures might be placed the same as with the other cores which would make it look similar with these high level die shots.
I don't know why people are looking so deeply into this. It's not even an actual photo of silicon.

Even their Tegra 2 "die shot" was doctored to hell.
 
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I don't know why people are looking so deeply into this. It's not even an actual photo of silicon.

Even their Tegra 2 "die shot" was doctored to hell.
I thought that was the point. Everything being identical shows it was doctored.
 
I seriously can't understand nV's "+1" core anymore, sure it made sense for last Tegra, but now ARM designed A7 or something as the companion core for A15's as in big.LITTLE designs, yet still nV has A15 +1

Seems like you really don't have an understanding in how 4+1 works. Nor an understanding of the die size cost penalties or royalties costs between the two designs.

Both 4+1 and big.LITTLE came about to keep power down when the devices were basically in standby mode or running very simple tasks. Who cares if a low power A15 (4+1) does the work or an A7 (big.LITTLE) the most important result is which uses less power overall.
 
The 5th core will still look different if analyzed at a low level, but memory structures might be placed the same as with the other cores which would make it look similar with these high level die shots.

Alright. That should be comprehensible if by the way it's all the same core so same pipelines, units etc.
I have trouble imagining what the low level optimization looks like.

No the 5th core is exactly like the other four it is just optimized with low leakage transistors and for lower clocks.

You know that what you quote says "It doesn't have different transistors like Tegra 2 and 3 had". Or well, I have to be partially wrong here. No "different" as in "mixed in from another process", but probably low leakage transistors (or gate) from the same process. Like in the transition from GF100 to GF110, if you wish. This is tricky, I hope I get it right that way.
 
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I seriously can't understand nV's "+1" core anymore, sure it made sense for last Tegra, but now ARM designed A7 or something as the companion core for A15's as in big.LITTLE designs, yet still nV has A15 +1

It's probably just a scheduling thing, big.LITTLE is fairly recent and Tegra 4 must have been in the pipeline for a long time.
 
Alright. That should be comprehensible if by the way it's all the same core so same pipelines, units etc.
I have trouble imagining what the low level optimization looks like.
There are many ways to implement the same function. For example, you can take the same design and synthesize it multiple times with different results. The same work would be done between pipe stages, but the way the gates are structured to accomplish the task will vary. This is due to an element of randomness in synthesis tools.

For those that don't know synthesis is the process of taking RTL (e.g. Verilog code) and converting it to logic gates.

I want to be clear that I'm not saying the end results will look drastically different just that they could look different.
 
I seriously can't understand nV's "+1" core anymore, sure it made sense for last Tegra, but now ARM designed A7 or something as the companion core for A15's as in big.LITTLE designs, yet still nV has A15 +1

Little BIG, is completely different, its' a 2x quadcore... one is 4xARM A9 ( A7v) + 4x ARM A15... Its not ARM who have design this, but Samsung.. Its a switch method, use low power cores for work on low power usage, and when you have the need of big power, it switch. ( im not sure how it will work on the benchmark generally used for tablet and smartphones anyway, because reviewers will need to know when it switch or not, or they will never been close of the reality in term of autonomy .

It will be interessant to compare both in term of Power consumption and power save, when both will be available on consumers products anyway.
 
Little BIG, is completely different, its' a 2x quadcore... one is 4xARM A9 ( A7v) + 4x ARM A15... Its not ARM who have design this, but Samsung.. Its a switch method, use low power cores for work on low power usage, and when you have the need of big power, it switch. ( im not sure how it will work on the benchmark generally used for tablet and smartphones anyway, because reviewers will need to know when it switch or not, or they will never been close of the reality in term of autonomy .

It will be interessant to compare both in term of Power consumption and power save, when both will be available on consumers products anyway.

Don't know about "Little BIG" but big.LITTLE is developed by ARM, not Samsung, and has Cortex-A15 and Cortex-A7, not A9. The configuration can be how many ever A15's paried with how many ever A7's.
A7 was specificly developed to be the "LITTLE" pair for A15
edit:
Oh, and recently they've announced A53 & A57 ARMv8 cores which are compatible with each other for big.LITTLE configurations, just like A15 and A7 are.
 
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