It depends on the type of memory.
So one rumor is massive transistor count (6T or 8T) or "true" SRAM. If that rumor is true there are a couple advantages of that route:
1. It is common practice to characterize a new process with a huge SRAM chip to gain yield information/drive yield improvement. (See the Intel test SRAM PDF)
2. It would be almost identical to L1 or L2 cache apart from the application. So very well understood and working fine on many other CPUs and APUs running in the same fabs.
3. SRAM is not the same tricky animal as eDRAM (or even worse FLASH) for gradients in process and temperature within a die. SRAM is actually much simpler and "relatively" trouble free compared with DRAM/eDRAM.
4. SRAM is used as L1 and L2 by IBM, Intel, AMD, everyone. It does not have problems in the applications with the big gradients across the die. Keep in mind true 6T/8T SRAM is digital output. There is no sense amplifier like there is in DRAM. And no similar FLASH wear nightmares especially with MLC.
Also look at the bank structure in the Intel die (PDF link below). A large SRAM is not a big monolithic block, it is subdivided into repeated smaller blocks. You can see that in AMD or Intel die photos too.
Next if it is on-die then the bandwidth could be extreme. (Could be and should be. If the bandwidth is low then it points to the strong possibility of off die like in the 360 eDRAM and then the yield and other rumors really make no sense.)
If it is off-die then the bandwidth is not as high but then the monolithic SOC is much smaller and yields are much much less of an issue. If off die we are at Sony APU size and no on-die eSRAM so the rumors and bashing can not be sustained.
Now there is another variant of the 32MB eSRAM rumor and the pros and cons should not be mixed. (I am seeing people pointing out all the bad possibilities of all of the combinations at the same time, that is illogical.)
The other variant is if the 32MB eSRAM is using "SRAM-like" eDRAM or 1T SRAM where it is really eDRAM (quite dense) and then there is a bunch of logic that makes that memory look like SRAM to the rest of the system. For example, it hides the refresh.
Note that there are many variants of these types of SRAM like DRAM. Many names and pros/cons.
So if this is the route then there are pros and cons:
1. The transistor count and die size is now much smaller (if on-die). So you can not add the "massive waste of die size and/or transistor count" of the 6T/8T possibility to the challenges of 1T SRAM or eDRAM. It is one or the other, not both.
2. On die it again can have very high bandwidth, so high that a system total of 200 GB/Sec look too low.
3. If it is off-die the APU is again smaller and much easier to yield. But the bandwidth goes down and the I/O power consumption jumps up.
4. Now to your question: Yes, if it is eDRAM/1T SRAM there can be problems with temperature and process variation. For example, if the array is too big and the variations (from process and/or temperature) are too high you can expect problems with leakage, sense amplifiers and error rates. So you have a sensitive "in a way analog" amplifier involved which is not involved in 6T or 8T. But you see they have known this for many years in the DRAM world and break things up into smaller blocks that look like tiles on a checker board if you look at a DRAM die shot. I think the wikipedia page for DRAM has a picture of a Micron DRAM die where you can easily see the structure if you want.
Here is the Intel PDF: Worth at least looking at the photos to see the subdivision in the structure of the memory array.
http://download.intel.com/pressroom/kits/events/idffall_2009/pdfs/IDF_MBohr_Briefing.pdf
