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Hardly think this matters anymore, if the only saving grace for the Xbox One is the cloud and it is taken away from them what is the reasoning for purchasing an Xbox One.....Kinect? Both MS and Sony scrambled after the success of the Wii and in my opinion it has been a waste of money (and i own the move
). MS and Sony should have just stuck to their guns and ignored the Wii like the consumers did after a while.
Thanks for making me laugh and shoot coffee all over my keyboard jerk!*
that was a good one
GrimThorne
Newcomer
It sounds great if you've been drinking.
You think the PS4 is a powerhouse console?!???
I think they both could have done better.
This is the exact point I was/am trying to make. Both MS and Sony have made in my opinion calculated sacrifices on the consoles due to the success of the Wii and the subsequent release of the WiiU. The only difference is Sony doesn't seem to have compromised as much as MS has but it is certainly seeming to be the strongest of the three by a fair margin.
But this is an Xbox thread and I don't really want to litter it with more PS4 stuff then necessary. The fact remains that things are not looking good for MS right now. The fact that rumors of downlocks are happening means more than if they are true or not. As it stands right now the consumers/fanboys/geeks are basically chicken little'ing the Xbox One because at this point any negative press seems likely to be true after the disappointing reveal.
MS needs to put a stop to this stuff ASAP before it spirals out of control. ANYTHING positive right now will do wonders for the machine. Don't wait until E3, show something positive now so the negativity stops. The Xbox One is a PR nightmare at this point and it really seems as though MS is not taking it seriously enough.
Averagejoe
Regular
If you actually mean by writing an article about this from a respected site,which involves any response from MS i say until hell freezes over,this is something that negatively impact their brand,don't spec MS to come clean on this.
They never ever did for RROD and that really need it a true explanation on their part.
That is what you think sony mess up big time but the PS was still by far the biggest brand on the console market so sony was able to get up and fight until the end.
We already know that MS wasn't able to keep the lead sales wise vs the PS3 in the end,so the 1 year head start didn't stop them,but we have see what happen when sony is the one with an advantage.
Also the things that make the xbox 360 popular,are not present on the xbox one,the console requires online,it has been fuzzy about used games,and the hardware inside is not comparable to a top en part on PC like the xbox 360 one was.
It is a very different scenario,alto nothing is warranty and anything can happen.
I doubt most people have ever heard of Crazy Butt Train or GAF so all this damaging PR is really a tempest in a teapot. If there is one thing you can count on from MS it is PR, I agree they have work cut out for them but they can manage.
Besides we don't even know its true...
Something like 8.5 million people watched the reveal. I'd be curious to know what percentage of those people were really disappointed with it. The Internet has a habit of magnifying some groups of people and making them seem a lot bigger than they really are.
There E3 show is named something like, "The Next Generation of Games Revealed." So I'm pretty sure the people who were upset by the reveal will be placated, in some sense. Now, if the games don't look all that great or exciting, then the problems won't go away. It'll be interesting to see what happens.
So far I haven't seen anything since the reveal to sway me a particular way. Kinect 2 actually is probably the most interesting part for me, mostly for fitness software and hopefully an incredibly awesome boxing game. Is that enough to get me to buy a console? Probably not. I'll stay on the wait and see approach.
Rumours of a downclock are not good. I'm taking them pretty lightly, only because I have no faith in most of the "insiders" especially gaf sources. There are a few people on this board that I'd take seriously if they confirmed it.
There E3 show is named something like, "The Next Generation of Games Revealed." So I'm pretty sure the people who were upset by the reveal will be placated, in some sense. Now, if the games don't look all that great or exciting, then the problems won't go away. It'll be interesting to see what happens.
So far I haven't seen anything since the reveal to sway me a particular way. Kinect 2 actually is probably the most interesting part for me, mostly for fitness software and hopefully an incredibly awesome boxing game. Is that enough to get me to buy a console? Probably not. I'll stay on the wait and see approach.
Rumours of a downclock are not good. I'm taking them pretty lightly, only because I have no faith in most of the "insiders" especially gaf sources. There are a few people on this board that I'd take seriously if they confirmed it.
Not sure about the percentage, but I felt a great disturbance on the Internet, as if millions of xbox fans cried out in terror and were suddenly silenced.
I think both Sony and MS have trouble ahead wrt games, the best of what we've seen so far is fairly derivative in terms of the actual gameplay and at worst the graphics have not been good enough to see the difference between current and next gen conclusively. Consumers are going to want to see a reason to buy the new thing especially if the new thing does a lot things I don't want like not play used games, force me to use motion controls and so on.
Personally this is why I think the independent developers to some degree are so important. Activision and EA are not going to do anything surprising, we can expect new Call of Duty and sports games from them. The production values will increase but the core mechanics are not likely to take many risk.
There is a reason why other entertainment mediums take breaks or shuffle line ups and I don't think the games industry has figured out how to do that yet.
Depends On Which Rumor: On Die Or Not, 6T/8T or 1T/eDRAM/etc
It depends on the type of memory.
So one rumor is massive transistor count (6T or 8T) or "true" SRAM. If that rumor is true there are a couple advantages of that route:
1. It is common practice to characterize a new process with a huge SRAM chip to gain yield information/drive yield improvement. (See the Intel test SRAM PDF)
2. It would be almost identical to L1 or L2 cache apart from the application. So very well understood and working fine on many other CPUs and APUs running in the same fabs.
3. SRAM is not the same tricky animal as eDRAM (or even worse FLASH) for gradients in process and temperature within a die. SRAM is actually much simpler and "relatively" trouble free compared with DRAM/eDRAM.
4. SRAM is used as L1 and L2 by IBM, Intel, AMD, everyone. It does not have problems in the applications with the big gradients across the die. Keep in mind true 6T/8T SRAM is digital output. There is no sense amplifier like there is in DRAM. And no similar FLASH wear nightmares especially with MLC.
Also look at the bank structure in the Intel die (PDF link below). A large SRAM is not a big monolithic block, it is subdivided into repeated smaller blocks. You can see that in AMD or Intel die photos too.
Next if it is on-die then the bandwidth could be extreme. (Could be and should be. If the bandwidth is low then it points to the strong possibility of off die like in the 360 eDRAM and then the yield and other rumors really make no sense.)
If it is off-die then the bandwidth is not as high but then the monolithic SOC is much smaller and yields are much much less of an issue. If off die we are at Sony APU size and no on-die eSRAM so the rumors and bashing can not be sustained.
Now there is another variant of the 32MB eSRAM rumor and the pros and cons should not be mixed. (I am seeing people pointing out all the bad possibilities of all of the combinations at the same time, that is illogical.)
The other variant is if the 32MB eSRAM is using "SRAM-like" eDRAM or 1T SRAM where it is really eDRAM (quite dense) and then there is a bunch of logic that makes that memory look like SRAM to the rest of the system. For example, it hides the refresh.
Note that there are many variants of these types of SRAM like DRAM. Many names and pros/cons.
So if this is the route then there are pros and cons:
1. The transistor count and die size is now much smaller (if on-die). So you can not add the "massive waste of die size and/or transistor count" of the 6T/8T possibility to the challenges of 1T SRAM or eDRAM. It is one or the other, not both.
2. On die it again can have very high bandwidth, so high that a system total of 200 GB/Sec look too low.
3. If it is off-die the APU is again smaller and much easier to yield. But the bandwidth goes down and the I/O power consumption jumps up.
4. Now to your question: Yes, if it is eDRAM/1T SRAM there can be problems with temperature and process variation. For example, if the array is too big and the variations (from process and/or temperature) are too high you can expect problems with leakage, sense amplifiers and error rates. So you have a sensitive "in a way analog" amplifier involved which is not involved in 6T or 8T. But you see they have known this for many years in the DRAM world and break things up into smaller blocks that look like tiles on a checker board if you look at a DRAM die shot. I think the wikipedia page for DRAM has a picture of a Micron DRAM die where you can easily see the structure if you want.
Here is the Intel PDF: Worth at least looking at the photos to see the subdivision in the structure of the memory array.
http://download.intel.com/pressroom/kits/events/idffall_2009/pdfs/IDF_MBohr_Briefing.pdf
It depends on the type of memory.
So one rumor is massive transistor count (6T or 8T) or "true" SRAM. If that rumor is true there are a couple advantages of that route:
1. It is common practice to characterize a new process with a huge SRAM chip to gain yield information/drive yield improvement. (See the Intel test SRAM PDF)
2. It would be almost identical to L1 or L2 cache apart from the application. So very well understood and working fine on many other CPUs and APUs running in the same fabs.
3. SRAM is not the same tricky animal as eDRAM (or even worse FLASH) for gradients in process and temperature within a die. SRAM is actually much simpler and "relatively" trouble free compared with DRAM/eDRAM.
4. SRAM is used as L1 and L2 by IBM, Intel, AMD, everyone. It does not have problems in the applications with the big gradients across the die. Keep in mind true 6T/8T SRAM is digital output. There is no sense amplifier like there is in DRAM. And no similar FLASH wear nightmares especially with MLC.
Also look at the bank structure in the Intel die (PDF link below). A large SRAM is not a big monolithic block, it is subdivided into repeated smaller blocks. You can see that in AMD or Intel die photos too.
Next if it is on-die then the bandwidth could be extreme. (Could be and should be. If the bandwidth is low then it points to the strong possibility of off die like in the 360 eDRAM and then the yield and other rumors really make no sense.)
If it is off-die then the bandwidth is not as high but then the monolithic SOC is much smaller and yields are much much less of an issue. If off die we are at Sony APU size and no on-die eSRAM so the rumors and bashing can not be sustained.
Now there is another variant of the 32MB eSRAM rumor and the pros and cons should not be mixed. (I am seeing people pointing out all the bad possibilities of all of the combinations at the same time, that is illogical.)
The other variant is if the 32MB eSRAM is using "SRAM-like" eDRAM or 1T SRAM where it is really eDRAM (quite dense) and then there is a bunch of logic that makes that memory look like SRAM to the rest of the system. For example, it hides the refresh.
Note that there are many variants of these types of SRAM like DRAM. Many names and pros/cons.
So if this is the route then there are pros and cons:
1. The transistor count and die size is now much smaller (if on-die). So you can not add the "massive waste of die size and/or transistor count" of the 6T/8T possibility to the challenges of 1T SRAM or eDRAM. It is one or the other, not both.
2. On die it again can have very high bandwidth, so high that a system total of 200 GB/Sec look too low.
3. If it is off-die the APU is again smaller and much easier to yield. But the bandwidth goes down and the I/O power consumption jumps up.
4. Now to your question: Yes, if it is eDRAM/1T SRAM there can be problems with temperature and process variation. For example, if the array is too big and the variations (from process and/or temperature) are too high you can expect problems with leakage, sense amplifiers and error rates. So you have a sensitive "in a way analog" amplifier involved which is not involved in 6T or 8T. But you see they have known this for many years in the DRAM world and break things up into smaller blocks that look like tiles on a checker board if you look at a DRAM die shot. I think the wikipedia page for DRAM has a picture of a Micron DRAM die where you can easily see the structure if you want.
Here is the Intel PDF: Worth at least looking at the photos to see the subdivision in the structure of the memory array.
http://download.intel.com/pressroom/kits/events/idffall_2009/pdfs/IDF_MBohr_Briefing.pdf
It does seem likely that a PS4 should be cheaper to make than a XBONE, dunno about the 8GB GDDR5 though.. but there is Kinect 2 and a big APU in the XBONE that needs money.. good for us that Microsoft has alot of money.. they can really give them away if needed. Another positive thing is that Sony wont be needing to bleed money to the same extent as they did with PS3.
A marathon with a half legged runner called Microsoft and well trimmed Sony. The gap in how games look can only grow as time goes by. With the PS3/360 it was very bad PR, late to market, high price and a HiDef war sponsored by Microsoft that made a very arrogant Sony humble again. If all these rumours are true it does seem as if Microsoft lost their way compared to the 360. And for many people it felt as if they had lost it before the underclock low yield rumours started.
Haha thought of the same thingWho would have thought 30 days ago that MS fans would actually be BEGGING for a 1.2TF GPU. What a brilliant fake downclock leak by MS.
I think they focused mostly on power pr watt, and they didn't do a bad job imho.
so true..cheers
HollovVpo1nt
Newcomer
Okay, I've been in touch with my contacts, and it turns out the downclock is true but not quite because of what people are thinking. It's not due to problems so much as a choice. Yields weren't great but enough for a decent launch. However, MS realised they didn't need so much power becauseof the POWER OF THE CLOUD!!!!
So are you trolling about there beeing a downclock or there beeing a downclock due to power of the cloud?
I can't handle this man, I can't fucking handle this shit.
Design Based Yield Techniques
Actually it does work with just one bin and is commonly done in the industry.
So if I were the design architect of the Xbox One SOC (and let us assume the 1.5 Billion transistor 6T or 8T on-die version of the rumors) here is what I would do and this is how the yield would be affected by fusing:
1. There would be spare CU units that could be fused off since this is as you said a one bin part.
2. The huge memory array would be broken up into smaller blocks. Since 32MB is so large I would have a space block. So the blocks would need to be small enough so that the penalty for fusing off one block is not so terrible on die size. For example, what if we have 33x1MB blocks and fuse off one? Of 66x0.5MB blocks and fuse off two?
3. Each block would have a spare rows/lines.
4. I might go so far as having an array 3x3 of the core (if it turns out to be the tiny jag) and then fuse one off. Most other people likely would not but I tend to be a bit nutty about yield and margins.
Take a look at the following link: It helps answer the question pretty well for you:
http://books.google.com/books?id=z-...page&q=spare word line for dram yield&f=false
That link talks about line and sub-array replacement.
I could lay out a similar rough plan for what could be done with eDRAM. I would be extra careful with eDRAM.
I am in a rush today so this might not be a great link but it talks about ECC for eDRAM:
http://www.nebrija.es/~jmaestro/esa/papers/IOLTS2012.pdf
ECC on MoSys 1T-SRAM:
http://www.storageforum.net/forum/s...ps-new-space-saving-way-to-add-ECC-on-1T-SRAM
Error Correcting (SRAM)
http://www.isi.edu/~draper/papers/esscirc08.pdf
Here is some good stuff:
1T SRAM is built as an array of small banks (typically 128 rows × 256 bits/row, 32 kilobits in total) coupled to a bank-sized SRAM cache and an intelligent controller. Although space-inefficient compared to regular DRAM, the short word lines allow much higher speeds, so the array can do a full sense and precharge (RAS cycle) per access, providing high-speed random access. Each access is to one bank, allowing unused banks to be refreshed at the same time. Additionally, each row read out of the active bank is copied to the bank-sized SRAM cache. In the event of repeated accesses to one bank, which would not allow time for refresh cycles, there are two options: either the accesses are all to different rows, in which case all rows will be refreshed automatically, or some rows are accessed repeatedly. In the latter case, the cache provides the data and allows time for an unused row of the active bank to be refreshed.
Original 1T-SRAM
About half the size of 6T-SRAM, less than half the power.
1T-SRAM-M
Variant with lower standby power consumption, for applications such as cell phones.
1T-SRAM-R
Incorporates ECC for lower soft error rates. To avoid an area penalty, it uses smaller bit cells, which have an inherently higher error rate, but the ECC more than makes up for that.
My point is that the industry has worked on DRAM *DESIGN BASED* yield improvement techniques for quite some time. DRAM and FLASH would cost quite a bit more without that.
I will see if I can dig up that IBM Power Point about the Power8. Might be a day or two until I find it again.
Actually it does work with just one bin and is commonly done in the industry.
So if I were the design architect of the Xbox One SOC (and let us assume the 1.5 Billion transistor 6T or 8T on-die version of the rumors) here is what I would do and this is how the yield would be affected by fusing:
1. There would be spare CU units that could be fused off since this is as you said a one bin part.
2. The huge memory array would be broken up into smaller blocks. Since 32MB is so large I would have a space block. So the blocks would need to be small enough so that the penalty for fusing off one block is not so terrible on die size. For example, what if we have 33x1MB blocks and fuse off one? Of 66x0.5MB blocks and fuse off two?
3. Each block would have a spare rows/lines.
4. I might go so far as having an array 3x3 of the core (if it turns out to be the tiny jag) and then fuse one off. Most other people likely would not but I tend to be a bit nutty about yield and margins.
Take a look at the following link: It helps answer the question pretty well for you:
http://books.google.com/books?id=z-...page&q=spare word line for dram yield&f=false
That link talks about line and sub-array replacement.
I could lay out a similar rough plan for what could be done with eDRAM. I would be extra careful with eDRAM.
I am in a rush today so this might not be a great link but it talks about ECC for eDRAM:
http://www.nebrija.es/~jmaestro/esa/papers/IOLTS2012.pdf
ECC on MoSys 1T-SRAM:
http://www.storageforum.net/forum/s...ps-new-space-saving-way-to-add-ECC-on-1T-SRAM
Error Correcting (SRAM)
http://www.isi.edu/~draper/papers/esscirc08.pdf
Here is some good stuff:
1T SRAM is built as an array of small banks (typically 128 rows × 256 bits/row, 32 kilobits in total) coupled to a bank-sized SRAM cache and an intelligent controller. Although space-inefficient compared to regular DRAM, the short word lines allow much higher speeds, so the array can do a full sense and precharge (RAS cycle) per access, providing high-speed random access. Each access is to one bank, allowing unused banks to be refreshed at the same time. Additionally, each row read out of the active bank is copied to the bank-sized SRAM cache. In the event of repeated accesses to one bank, which would not allow time for refresh cycles, there are two options: either the accesses are all to different rows, in which case all rows will be refreshed automatically, or some rows are accessed repeatedly. In the latter case, the cache provides the data and allows time for an unused row of the active bank to be refreshed.
Original 1T-SRAM
About half the size of 6T-SRAM, less than half the power.
1T-SRAM-M
Variant with lower standby power consumption, for applications such as cell phones.
1T-SRAM-R
Incorporates ECC for lower soft error rates. To avoid an area penalty, it uses smaller bit cells, which have an inherently higher error rate, but the ECC more than makes up for that.
My point is that the industry has worked on DRAM *DESIGN BASED* yield improvement techniques for quite some time. DRAM and FLASH would cost quite a bit more without that.
I will see if I can dig up that IBM Power Point about the Power8. Might be a day or two until I find it again.
D
Deleted member 7537
Guest
http://www.neogaf.com/forum/showpost.php?p=61427697&postcount=1743
According to neogaf mods he is legit. But no official confirmation.
Gradthrawn
Veteran
Okay, I've been in touch with my contacts, and it turns out the downclock is true but not quite because of what people are thinking. It's not due to problems so much as a choice. Yields weren't great but enough for a decent launch. However, MS realised they didn't need so much power becauseof the POWER OF THE CLOUD!!!!
Triple nested spoilers, well done sir.
GrimThorne
Newcomer
I wasn't making any comparisons, I'm just disappointed with both platforms this generation. Both Microsoft and Sony went for the lowest hanging fruit. I'm beginning to understand both Microsoft AND Sony's silence. Because Sony isn't talking either. They've cleverly stood behind Microsoft while everyone throws eggs and rocks at them, but there's a good chance they're using the same play book on used games, DRM etc.
As for the Xbox One. *sigh* For all the claims about cloud power, IBM SoC teams and special silicon etc. I don't know who these people are, but they need to understand that they built a lousy piece of engineering. So lousy that it even needs to be downclocked because it can't even deal with it's own meagerness.
Large last-level storage arrays tend to favor density more heavily. One of AMD's bugbears for quite some time was their being forced to use L2 arrays in the L3, which significantly impacted density.
Cells in cache arrays are linked to long shared bit lines. There are sense amps in caches as well, if only to keep read times fast.
There are pictures of the Xbox One's innards, there is no secondary die. Microsoft did mention a very high aggregate transistor count for the system, although I haven't found a quote that directly mentioned the eSRAM by name outside of third-party sites that may be drawing data from VGleaks.
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