IBM Virtual Vector Architecture: IBM refuses vector process

[Deadmeat]

http://www.nersc.gov/news/blueplanetmore.html

The Virtual Vector Architecture
The basic intent of the Virtual Vector Architecture (ViVA) facility is to allow customers/ applications to run high performance parallel/vector style code on a traditional high data bandwidth SMP. What is described below is currently an unsupported function within IBM, involving compilers, operating systems, Hypervisors, firmware, processor/systems, and productization. On the positive side, the Power 5 processor/system design does have basic functionality to support ViVA.

ViVA would further enhance the Blue Planet system and take IBM in a new direction. Power 5 chips have the ability to synchronize the CPUs using a hardware communication link for barrier synchronization. This hardware feature is currently not planned for exploitation because there is not an identified requirement within the existing markets. However, the synchronization feature can be used to harness individual CPUs into a "virtual vector" unit. This is the same concept implemented in the Cray X1 MSP CPU, which has four separate 3.2 Gflop/s SSPs that synchronize for vector processing.

The basic intent of ViVA is to allow customers/applications to run high performance parallel/vector style code on a traditional high data bandwidth SMP. Initially, ViVA’s goal is not to improve memory bandwidth per se. It does greatly enhance the ability of compilers (and programmers) to exploit fine-grained parallelism automatically, as is done with compilers that run on existing vector systems. The result should be to increase the proportion of applications that have higher sustained performance, thereby making the system much more cost effective for a wider range of scientific applications.

ViVA will be implemented on the Blue Planet system through software that uses the Power 5 architectural features. It will be evaluated and available to the applications that benefit from it. If the evaluation and use of ViVA shows benefit, not only will it enhance application performance of Blue Planet beyond what is described above, but it is conceivable that further vector-like support will be possible in future generations of the IBM Power architecture. If the ViVA experiment is not as successful, Blue Planet will perform with no lower performance than that described above.

I keep telling this you over and over : IBM doesn't build real vector processors... At rumored 24 million transistors each, VMX2 has no place in XCPU2(Eats up too much transistors) and MS will not pay for the cost of two. XCPU2 will be a die shrunk 65 nm Power5 minus cache, no more no less.

 

[Deadmeat]

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I wonder why I never heard about this feature before.

Maybe this is what Jim Kahle(CELL chief architect) meant when CELL was based on Power4 but "evolved" differently? That individual CELL cores are really Power cores that two of them can link to form a virtual vector processor at will? This way CELL can adapt itself to both scalar code and vector code as needed without having dedicated vector units??

Fascinating....

 

[Megadrive1988]

XCPU2 will be a die shrunk 65 nm Power5 minus cache, no more no less.

so you're saying XCPU2 will be one processor die, with two cores (because that's what Power5 is, right) and no cache, or less cache?
it has to have *some* cache....XCPU had half the cache of a normal Pentium 3 Coppermine...

 

[Deadmeat]

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so you're saying XCPU2 will be one processor die, with two cores (because that's what Power5 is, right) and no cache, or less cache?
it has to have *some* cache....XCPU had half the cache of a normal Pentium 3 Coppermine...

Who knows, IBM might be offering the same unknown 64-bit PPC core(I doubt it is a straight Power, but some kind of consumer oriented low cost core) design to both SCEI and MS, and that each customer may choose to implement as many cores as needed. SCEI could have taken 8, while MS could have settled for four and save money.

At least this description of ViVA is much more in line with Kahle's description of CELL in the past. Kahle's description of CELL was multiple general purpose processors packed on a chip, not the PE+APU thing that we are familiar with.

 

[Deadmeat]

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Read this if you can read Japanese

In that article, there is an interview with Dr. Dr. Frank Soltis who overseas AS/400 program. He claimed that Power5 tech would show up on both CELL and Xbox. While it made sense why Power5 would show up on Xbox, it was never clear to me why Power5 would also show up on CELL, given the PE+APU description in that SCEI patent application. Unless what we knew about CELL was all-wrong in the first place...

Then you have people like Jim Kahle whoses past description of CELL(a chip with 4~16 general purpose processors packed in. a Power4 derivative) was very different from the one described in SCEI patent application.

So my conclusion at this point is that PE+APU architecture(A Super Emotion Engine) was Kutaragi's initial purposal that was rejected by Kahle, and IBM engineers went their way with CELL afterward. So the real CELL we will see this summer is likely be a consumer oriented PowerPC core with the ability to chain themselves to form a virtual vector unit at will.