Details trickle out on CELL processor...

Cryect said:
Basically cheap for their performance, a DSP is an example of a fixed function stream processor where everything has been prespecified. Stream processors can be setup to allow programming but are often fairly limited. Basically stream processors are good if you need a specified processing rate for a fixed maximum amount of data bandwidth (example a router).
So a regular general purpose CPU (or SIMD vector PU, like an APU) could be setup to do both stream processing and normal chunked, only it wouldn't use its cache or SRAM fully?
 
So a regular general purpose CPU (or SIMD vector PU, like an APU) could be setup to do both stream processing and normal chunked, only it wouldn't use its cache or SRAM fully?

Its call general purpose because it is general purpose. A stream processor however can not be made into general purpose processor. For example take a vertex shader in Xbox or R420, if you submit 4 vertices to it, it will process those vertices according to the instruction and will output 4 vertices.

On the other hand the VU in PS2 EE, you can give it several values and instructions and it can generate many vertices from them.

Those two sites refer to the APUs as stream processors, if it is really a stream processor than it might not be able to generate new data like vertices or pixels. Everything needs to be generated in the PU and send to those APUs for further processing.
 
eh , i will wait till we see actual performance out of these things .

Last generation with sony it was best to divide what they said by 3 and you'd get final output give or take a bit .
 
bbot said:
Remember this?

Look how many chips on a rack there are (64 chips), each chip having 32 cells on them?

Yes and I still fail to see the connection, just as I did last night preventing me from posting it.

bbot said:
Turns out its only 8X more powerful than expected. So one cell = 8Gflops instead of 1 Gflops? And I thought cell would first use 65nm tech? Now who's the one who said that (cough, cough) :) ?


First off, what are you talking about? What's rated at 1 or 8 GFlop exactly?

Secondly, it will use 65nm in the shipping version. The reports have stated that it has already sampled and is undergoing testing. STI is gearing up for 65nm. 90nm is a tranistory node that may get used in CE and/or IBM server's in the intermediate.

I fail to see a single seminal or otherwise logical comment in this post.
 
bbot said:
Remember this?

NO!

That is blue gene you see on that slide! Not Cell!

It's been relabeled, that's all. It illustrates blue gene, and it's a blue gene presentation it originates from.
 
Look how many chips on a rack there are (64 chips), each chip having 32 cells on them?

There are smaller rack you know.

And I thought cell would first use 65nm tech? Now who's the one who said that (cough, cough)

This one is still in prototype stage. Consumer product would use 65nm tech to lower cost, I belive.
 
V3 said:
Those two sites refer to the APUs as stream processors, if it is really a stream processor than it might not be able to generate new data like vertices or pixels. Everything needs to be generated in the PU and send to those APUs for further processing.
Sorry, but this really doesn't make any sense. It's a completely arbitrary restriction, imho. Even a so called stream processor (by your defintion) like a
vertex shader engine could kill triangles by collapsing different vertices in degenerate primitives. Are pixel shaders hw implementations on current GPUs stream processors?
I believe they are..but they can arbitrarily kill pixels! Or we can render pixels into vertex buffers and create new geometry :)
 
Sony said it would launch home servers and high-definition televisions powered by Cell in 2006, and reiterated plans to use the microchip to power the next-generation PlayStation game console, a working version of which will be unveiled in May.
:p
 
DaveBaumann said:
http://finance.yahoo.com/mp#rmbs

10:23AM Mike Tarsala's TechWatch Alert -- RMBS (RMBS) 24.34 +2.17: Analysts we reached this morning say that Rambus is very likely to benefit from the Cell processor announced today by Sony (SNE), IBM (IBM) and Toshiba (TOSBF). Of note, Rambus announced back in January 2003 that it had licensed its XDR memory and its Redwood high-speed parallel interface (its Yellowstone and Redwood technologies) to Sony and Toshiba. While IBM was NOT MENTIONED in that 2003 release, Big Blue is known for having a strict approval process when its name appears in other company's press releases. Another company analysts have mentioned as possible benefactor from the Cell processor, which is expected to go toe-to-toe with Intel in the home entertainment (specifically the multimedia living room) could be graphics-processor maker Nvidia (NVDA) -- although none of the analysts offered any specific proof. More details on the Cell processor are expected to be announced at the International Solid State Circuits Conference, which is scheduled to begin on Feb. 6 in San Francisco.


PS3 = POWER CPU + Nvidia GPU + Linux OS + OpenGL

XB2= POWER CPU + ATI GPU + Windows OS + WGF
 
Cell Performance

Hello,

In looking at all these replies to the cell article, I feel that I should respond to some of these posts:

It's official - Deadmeat = Mr.Zimmon.

No no. I don't know who this Deadmeat person is. I hope there is no confusion now.

Is zimmon's talking about on chip or off chip memory speed?

I am referring to main memory bandwidth to the processors (off chip).

"The PS3 memory is rumored to be able to transfer around 100 Gbytes/second, which would mean it could process new data at roughly 25 Gflops (at 32 bits) — far from the 1-Tflops number."

Unfortunately, I didn't really relate that this is my *worst* case estimate of PS3 performance i.e. with no cache and empty SRAM APU memories. We don't really know what the final configuration will be capable of but in the *worst* case it will be probably be above 25Gflops.

The NV40 is somewhere around 200 Gflops but using the Brook language shows an actual calculation rate of around 40 Gflops for regular non-graphics computation. Blue Gene is targeted at 3Pflop with 1Pflop sustained.

For data that fits in the cache + SRAMs then the performance is easily in the 100s of Gflops. For "real world" calculation maybe 300 Gflops is reasonable?

Again, I am not 100% sure. No one is. But I hope that I have helped give a more accurate picture of what I was trying to say.

With such small on-chip memories and such huge processing horsepower, is ray tracing or some form of GI inevitable?
 
Re: Cell Performance

PZ said:
With such small on-chip memories and such huge processing horsepower, is ray tracing or some form of GI inevitable?

I'm pretty sure they will go for hardware accelerated software realtime rendering as described in one of the patents that where posted here and I think that MS and Nintendo will go that route one generation later and now stick with a shader GPU for next gen. I still think the final PS3 could reach 1TFlops, but only if they get the 65nm tech right, they just can't wait till 2007 if they run into problems.

Fredi
 
With nVidia and Microsoft so quick to part ways despite being mutually beneficial to each other and with the stage set for a more specialized graphics part for PS3, I'm wondering if Sony isn't providing nVidia with business by buying some of their graphics tech off of them this time.
 
I don't see what the facination is with the need for realtime ray tracing. For offline rendering, you really don't need ray tracing to have a good quality end result. Hasn't pixar proved that over and over again?

btw what exactly has been determined about cell in this thread? anything?
 
1st generation Cell Processor, 90nm SOI.
  • 4.6GHz global PE clock speed
    [list:61b5dc9276]
  • 1.3V
  • 85deg C w/ heatsink
  • 6.4Gbit/pin external communication
  • 6.4GHz/link RaZer internal bus
[*]64-bit Power-based PU
  • SMT, CMP
[*]DMAC intensive, software driven RT arbitration of resources
[*]S|APUs
  • upto 8/PU
  • 4 FPUs
  • 4 FXUs
  • 128*128bit Registers
  • 128KB of LS (SRAM) @ 4.8GHz
    [list:61b5dc9276]
  • 1.2->2.4TByte/sec bandwith*
[/list:u:61b5dc9276]
[*] Second generation, 65nm Cell Processor has already sampled
[*] 15TFlop/sec DevKits have been sent out[/list:u:61b5dc9276]

The above was presented at ISCC and based off the 90nm silicon that's in existence. What is likely extrapolated from this:

2nd generation Cell Processor, 65nm SOI.
  • >4GHz clock
    [list:61b5dc9276]
  • 1-4 PE's per IC
  • 8 S|APUs per PE
    [list:61b5dc9276]
  • 256GFlop -> 1.3TFlop/sec FP
  • 1.2TByte/sec -> ~10TByte/sec bandwith to LS*
[/list:u:61b5dc9276][/list:u:61b5dc9276]
Fill in what I missed.

*Upper number dependent on single cycle read/write like in EE VU's
 
Qroach said:
What about time frame, have they produced the workstations yet? or has that been pushed to next year?

Read what I wrote Q, it's in there. HINT: Next to the 15TFlop/sec number. As stated, they've had 90nm, 1st generation Cell Processors for some time and kits built off them -- obviously this is fact as the ISSCC concurs. They have been sampling 65nm (confirmed) and I heard it's been since summer. 65nm production has been stated as 1H2005. Try not to invent bad things...
 
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