10.2 The Design and Implementation of a First-Generation CELL Processor
9:00 AM
D. Pham(1), S.Asano(2),M. Bolliger(1), M. Day(1) , H. Hofstee(1), C. Johns(1) , J. Kahle(1) , A. Kameyama(3) , J. Keaty(1),Y. Masubuchi(2), M. Riley(1), D. Shippy(1), D. Stasiak(1) , M.Wang(1) , J.Warnock(1), S.Weitzel(1), D.Wendel(1) , T.Yamazaki(1) , K.Yazawa(2)
1 - IBM, Austin, TX
2 - Sony, Tokyo, Japan
3 - Toshiba, Austin, TX
A CELL Processor is a multi-core chip consisting of a 64b Power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high-frequency clock-rate.