Details trickle out on CELL processor...

things seem to be following a very similar pattern to how PS2 info came out.

in late 1998 (like late Nov, early Dec 2004 now) there were a few bits of info that came out on the PS2 processor, what would be the EE, if you recall.

Performance Refresh In one ISSCC paper, Toshiba and Sony will describe a
17-by-14.1-millimeter device consisting of a 250-MHz MIPS CPU core with
128-bit multimedia extensions, 10 floating-point multiplier accumulators
(MACs), four floating-point dividers, an MPEG-2 decoder, a 10-channel DMA
controller, and other peripherals -- all linked together by 128-bit
internal buses. [/b]
then in Jan or Feb 1999, at one of the chip conferences (maybe the same one that happens in Feb 2005) we got more info on PS2 processor. then March 1999 we got full PS2 spec including the 50 MHz bump in EE clockspeed (GS might have been upped also but no info on GS came out before March 99).



edit: look here

this is from November 1998

http://groups.google.com/groups?hl=...9-1311980255490001@d3.dial-1.wal.ma.ultra.net

Subject: PSX 2: Get Ready For Real 128 Bit Power
View: Complete Thread (12 articles)
Original Format
Newsgroups: rec.games.video.sony, rec.games.video.sega, rec.games.video.nintendo
Date: 1998/11/13

Toshiba Processor May Be Brains Of PlayStation
(11/12/98 10:53 a.m. ET)
By Anthony Cataldo and David Lammers, EE Times

Sony Computer Entertainment and Toshiba will soon announce research on a
jointly developed media processor that may provide the first glimpse at
the embedded hardware for the next version of Sony's wildly successful
PlayStation.

At the International Solid State Circuits Conference next February, the
companies will together present two papers describing a multimedia
processor. Although neither company would comment on how their development
work will play out in the market, rumors have been swirling for some time
that they have been cooperating on a next-generation game console.
The
ISSCC papers offer the first peek at jointly developed silicon that could
be used for such a platform.

PlayStation is a coveted system win among IC makers, and Toshiba's coup
reflects that company's growing prowess in the system-on-a-chip era. But
the high-profile work apparently will not bump LSI Logic Inc. (LSI) out of
its PlayStation sockets.

Elie Antoun, an LSI vice president in charge of consumer IC product
development, said his understanding is Toshiba silicon will reside
alongside ASICs from LSI Logic in the next go-round.

"I can't exactly comment, but the anecdotal evidence is Toshiba silicon
may be in there, too," said Antoun, who until last summer, was president
of LSI Logic's Japan subsidiary. "I am highly confident ASICs from LSI
will be there. We are designing something quite significant that will go
in that [next-generation] box, but who else is in the box I cannot say."

Although LSI Logic, in Milpitas, Calif., may continue to be a player, it
appears the company may not dominate the next-generation PlayStation the
way it did the first, introduced about five years ago. At that time, the
gut-wrenching effects produced by the driving game Ridge Racer, combined
with the silicon from LSI, took the game market by storm.

At the Interactive Digital Media Association convention in Orlando, Fla.,
last month, a Sony representative said the company is making an astounding
2 million PlayStations a month. Having dropped the hardware price to $129,
Sony makes much of its overall profits by licensing and selling games to
run on the CD-based system.


Performance Refresh In one ISSCC paper, Toshiba and Sony will describe a
17-by-14.1-millimeter device consisting of a 250-MHz MIPS CPU core with
128-bit multimedia extensions, 10 floating-point multiplier accumulators
(MACs), four floating-point dividers, an MPEG-2 decoder, a 10-channel DMA
controller, and other peripherals -- all linked together by 128-bit
internal buses.


The 0.18-micron, 1.8-V device packs 10.5 million transistors and
dissipates 15 watts.

The second paper describes in more detail the 10.9-by-6.3-mm CPU block
that is the nucleus of the multimedia chip. This MIPS-compatible CPU is a
two-way, superscalar architecture with 8 kilobytes of D-cache, 16 KB of
I-cache, and 1-k-by-128 bits of scratch-pad RAM tightly coupled to the
pipe and 128-bit internal data paths. The CPU is capable of executing more
than 100 multimedia instructions.

"The embedded MPU processor was developed by Toshiba, and the interface
technology was developed by Sony," said Yoichi Unno, general manager of
Toshiba's microelectronics engineering laboratory. He said Toshiba and
Sony have had a working relationship for the past three years.

Unno would not comment on whether the media processor was intended for
Sony's next-generation game console, but he did say the two companies
intend to make a public announcement in February regarding their
partnership. A Toshiba spokesman said the announcement could come weeks
before ISSCC or during the conference, which will be held in San Francisco
Feb. 15 to 17, 1999.

Because ISSCC prohibits companies from fully disclosing papers before the
their formal presentation, no further details about the chip's features
were publicly available.

Even so, the basic description indicates an architecture that uses both
hardwired, distributed processing and software-based processing. It makes
wide use of hardwired blocks such as independent MACs and a separate
MPEG-2 decoder connected by wide 128-bit internal buses, yet it also
leverages the CPU to execute special multimedia instructions.

Such a heavy reliance on CPU power would be a departure from Sony's
single-chip device, co-developed with LSI Logic. That part has been
described by those involved as an exemplary case of a
distributed-processing design.

Even though it uses a relatively slow 34-MHz CPU, the processor in the
original PlayStation is able to eke out 220 MIPS by placing much of the
burden on bus and memory-access channels to enable simultaneous operation
among the various functional blocks. A separate graphics processing unit
brings the total processing power to 500 MIPS.

However, in the four years since the last PlayStation hardware
architecture came to light, advances in process technology and CPU speeds
have made software-oriented computing more practical. The use of
multimedia instructions, as described in the ISSCC summary, would indicate
a greater reliance on CPU power.

Indeed, Toshiba engineers have said they are starting to put more weight
on utilizing the power of faster on-chip CPU to carry much of the
processing load rather than relying solely on dedicated functional blocks.
Such a sentiment has been echoed by engineers at companies such as NEC.

In a recent interview, Toshiba engineers outlined a plan to couple
hardwired intellectual-property blocks and embedded software designed to
take advantage of fast embedded MPUs as the best recipe for
system-on-a-chip design.

"We're going to provide hardware and software intellectual-property cores
in parallel," said Atsushi Tanaka, a specialist with the
intellectual-property planning section at Toshiba's IC Center, in
Kawasaki, Japan, a division of the microelectronics group working with
Sony. "The performance of the MPU is increasing rapidly, and every year,
more and more tasks can be accomplished by software."

As for graphics, neither of the two ISSCC papers from Toshiba and Sony
makes mention of 3-D processing functionality, which could indicate those
tasks will fall to a separate processor. That would make sense, because
any high-performance 3-D engine is probably still too transistor-laden to
be absorbed into a general-purpose media processor, said Michito Kimura,
an analyst with International Data Corp. (IDC), in Tokyo.

"I think the chip size would be too big," he said. "Maybe it will be
possible by 2002 or 2003."

What is known about Sony's 3-D plans is the company will depart from
polygon-based 3-D graphics now used in the PC world. Instead, it will
develop a new generation of real-time image-rendering technologies that
will encompass a new breed silicon, platform algorithms, and software
titles.

There's also strong evidence that by including an MPEG-2 decoder engine
on-chip, Sony may be aiming to incorporate video-processing, such as DVD,
in its future platform. The company already uses optical-disk media for
PlayStation, and some believe moving to DVD would be a natural next step.

"The new trend will be DVD versions of game consoles," said IDC's Kimura.

Kimura added Sony's group has been vocal about its desire to couple
embedded DRAM with 3-D processing, another area where Toshiba has
strength.

When it dropped out of the three-way DRAM venture co-sponsored by IBM and
Siemens, Toshiba brought back a group of DRAM design engineers and put
many of them to work on developing a "merged" DRAM-in-logic process.
Toshiba has used that technology in its ASIC business. Also, the company
has converted a DRAM fab at its complex in Oita, Japan, and upgraded it to
0.25-micron merged process capabilities.

LSI Logic, too, is working on embedded DRAM, in tandem with Micron
Technology, in Boise, Idaho. With the development phase drawing to an end,
LSI said it expects to have merged DRAM capabilities in its arsenal by
mid-1999. But that may be too late for the chip set being developed for
the next-generation PlayStation.

Sources said Toshiba initially got its foot in the door at Sony, the most
sought-after electronics customer among Japan's IC companies, after it was
chosen to design a gate array that now serves as glue logic in the current
PlayStation.

Toshiba's apparent success in working with Sony for such a high-profile
consumer product is a testament to how strong a contender Toshiba's
system-on-a-chip business has become in recent years.

"Toshiba is and will be a major player and is a formidable force in
system-on-a-chip," said Jan Goodsell, a Tokyo-based consultant who
represents third-party intellectual-property suppliers. "They have huge
resources and work well with a lot of third parties. They have the
technical resources and a lot of intellectual property."

Nearly every IC vendor covets the Sony PlayStation business. When Brian
Halla, CEO of National Semiconductor, took the stage at the Microprocessor
Forum in San Jose, Calif., last month, he immediately asked Ken Kutaragi,
in charge of chip development at Sony Computer Entertainment, to stand up
and take a bow.

google groups hits on same/similar info.
http://groups.google.com/groups?num...mp;as_maxd=31&as_maxm=11&as_maxy=1998
 
Dr. Gschwind is one of the originators of the STI CELL Broadband Architecture and was a member of the joint architecture exploration and definition team. He was also the leading architect of the SPU architecture and the instigator of its compiled code SIMD focus. Dr. Gschwind was the developer of the first compiler targeting the BPA. His contributions to the S/T/I project were recognized with an IBM Research Achievement Award.
What's BPA? Is it something related to compilers technology?
EDIT: at least this time Sony (well..IBM :) ) is addressing the compiler technology problem!
 
one, yes I know you mentioned this before me, but I wanted to mention it also.

and also, I felt I needed to mention the late 1998 info on EE/PS2 is paralleling the late 2004 info on CELL/PS3 :p which you did not include..

all is cool, right? 8)
 
It's very interesting how they mentioned LSI Logic back then. Was it known that PS2 had backward compatibility?
 
What would be fundamentally wrong with that?
At the end of the day, Sony didn't lie, from the beginning they said PS2 is capable of rendering 75 (or 66?) million flatshaded poligons per second when nothing else is being processed. And it's true. Useless to know, but it's true.
They also said real world numbers would be much lower, and in the region of 10-20 million maximum in a real game, which is also true.

Or shall we stqart on the numbers MS gave before launching the Xbox? The 300million polys, then downgraded to, what was it, 150 or something...

Everyone does it. The only ones not to brag about "theoretical" numbers this generation was Nintendo, Kudos to them.

officially:
*PS2's EE could calculate / process / compute 66 million polygons per sec
*PS2's GS could draw / render / display 75 million flat shaded polygons per sec
*PS2 could display around 25 million textured, z-buffered, alpha blended (and gouraud shaded?) polygons per sec


Microsoft's figures were indeed actually more misleading.

especially the 300 million micro-polygons/sec and 150 million t&led polygons/sec as well as the 4.8 billion pixel per second fillrate with 2 textures applied.

turns out the final Xbox was 116 million polygons/sec (flat shaded?) and 932 million pixels/sec
 
Cryect said:
Edit 6: Page 77

28.9 Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor
4:45 PM
K. Chang(1), S. Pamarti(1), K. Kaviani(1), E. Alon(1),(2), X. Shi(1), T. Chin(1), J. Shen(1), G.Yip(1), C. Madden(1), R. Schmitt(1), C.Yuan(1), F. Assaderaghi(1), M. Horowitz(1),(2)

1 - Rambus, Los Altos, CA
2 - Stanford University, Stanford, CA

A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. A clock-tracking architecture suppresses reference jitter to achieve 6.4Gb/s/link operation at 21.6mW/Gb/s. SOI effects on analog circuits, in particular high-speed receivers, are addressed to achieve a receiver sensitivity of ±12mV at 6.4Gb/s with BER <10-14 measured using 7b PRBS data.

Here is Mark Howowitz's web page.

http://www-flash.stanford.edu/~horowitz/


Some might find this intresting. It has some info on Stream Processing.

Architectures, Languages, and Compilers for the Streaming Domain
 
The intriguing thing is that the ISSCC 2005 paper reports so far don't seem to mention anything about a Cell Visulaizer (aka Realizer) type GPU/Rasterizer...hmm :?

Jaws, this might not be relavant to today, but back in late 1998 when info on what would be the Emotion Engine CPU came out, there was NO info at all on PS2's graphics chip.

http://groups.google.com/groups?selm=19981110072147.19871.00006628@ng126.aol.com&output=gplain


November 09, 1998
Missing from this equation is the 3D-specific hardware that will be
required to render the aforementioned mass of processing-intensive NURB
polygons. While the DSP would likely be able to compute them all, it
certainly isn't the square of silicon that will eventually slap them on
the screen. That's where a dedicated 3D processor would come in. And it
ain't here. Also nowhere to be found is the dedicated sound processor
that any current-day console wouldn't be caught without.

I'm not at all worried that PS3 won't have a seperate graphics processor of some sort with some hardwired 3D functions. be it Graphics Synthesizer 3, Visualizer, Realizer, etc.
 
oh btw, heh, the 15 or 16 TFLOPs Cell WorkStations that'll supposedly come out sometime down the road (2005-2006) in theory well surpass the infamous "1000x PS2" comments from KK back in 1999. by more than 2x :oops:

I know we're dreaming of an 8 TFLOPs CPU in PS3 right now, half as much as a 2nd generation Cell workstation, even though were far more likely to get a 500~600 GFLOPs CPU in PS3 :?


still, 100x more theoretical power than PS2 isnt too bad!
 
The SPU is the new Power PC 300 series as that was reported as a rumor a while back on Apple Insider in December of 2003. This will replace the Power PC 400 series they sold off to Applied Micro Circuits.

Applied Micro Circuits Corporation announces definitive agreement to acquire intellectual property and a portfolio of PowerPC® 400 products from IBM, signs Power Architecture™ license

The PowerPC 300 series is what Sony and Toshiba got from the "CELL deal". Anytime they embed this into a product they probably don't have to pay a royalty to IBM. Something that I feel backs up this logic is when Sony Group licenses IBM Power Architecture-based chip technology was announced back in March. Toshiba hasn't done a similar deal because at this time they have no use for a general purpose processor, they're just going to embed the 350 into all sort of devices. If you're going to put a processor into a cellphone or HDTV, you won't put something big and power hungry like a Power 4 along with some SPU's (Power 350's). Sony has to have the additional POWER license because they need it for Workstations and the Playstation 3.

I'm not saying this is fact, just the conslusion I have reached after reading all the press releases and rumors. Also I'm starting to believe Deadmeat is right about the clockspeed. The SPU is 1.15 Ghz, not the 4.6 Ghz. Thet 4.60 Ghz clock speed would be so far beyond any other competitor that it's just getting too hard to believe.
 
Brimstone said:
Fox5 said:
http://ps2.gamespy.com/playstation-3/avalon/569218p1.html

The Cell is a multicore chip comprising a 64-bit Power processor core and is optimized for compute-intensive workloads and broadband rich media applications, including computer entertainment, movies and other forms of digital content. The Cell chip will be able to support multiple operating systems at the same time, and will feature a flexible on-chip I/O (input/output) interface.

I thought cell wasn't supposed to be a Power processor?

It seems that CELL is just a codename. Microsoft and Nintendo have the same acess to all the work Sony, Toshiba, and IBM have done over the last 5 years with regards to CPU architechture. Microsoft and Nintendo aren't intrested in the scalable aspect of the POWER core, since they just want it for one basic use and they don't fab their own semiconductors like STI.

Why not use an athlon 64 for scalability? AMD seems to be further ahead with up to 8 chips each 1 a dual core operating together. Or are Power processors cheaper?(or would amd be unable to meet demand?)

Then, it's very natural they chose IBM as the first company which reached 1Ghz back in 1998.

What chip did they have that reached 1ghz(I'm guessing it wasn't powerpc as in the consumer market that reached 1ghz way after the athlon and pentium 3)? And more importantly how did it perform, and what was its power consumption and heat dissapation?

especially the 300 million micro-polygons/sec and 150 million t&led polygons/sec as well as the 4.8 billion pixel per second fillrate with 2 textures applied.

turns out the final Xbox was 116 million polygons/sec (flat shaded?) and 932 million pixels/sec

Wasn't the 4.8 billion at a higher clock rate and counting antialiasing as additional fillrate for free?

This will replace the Power PC 400 series they sold off to Applied Micro Devices.

What's AMD going to do with a PowerPC series? Rip it apart and copy the design?
 
Brimstone said:
Also I'm starting to believe Deadmeat is right about the clockspeed.

Why? DM's just talking outta his ass and pulling his numbers from the same place actually. Just like always, he's had so many versions of "Cell" as he insists on calling it (rather than broadband engine, which is what'll end up in PS3).

The SPU is 1.15 Ghz, not the 4.6 Ghz.

What makes you so sure?

Why would they run the processor itself at a quarter speed of the cache memory anyway? That makes no sense, it'd be much easier to make the SRAM wider rather than faster if bandwidth was an issue.
 
Guden Oden said:
Brimstone said:
Also I'm starting to believe Deadmeat is right about the clockspeed.

Why? DM's just talking outta his ass and pulling his numbers from the same place actually. Just like always, he's had so many versions of "Cell" as he insists on calling it (rather than broadband engine, which is what'll end up in PS3).

The SPU is 1.15 Ghz, not the 4.6 Ghz.

What makes you so sure?

Why would they run the processor itself at a quarter speed of the cache memory anyway? That makes no sense, it'd be much easier to make the SRAM wider rather than faster if bandwidth was an issue.



That is an incredible clock speed. I don't think there is anything even remotely close to that speed in DSP's, CPU's, or whatever.


Also Fox5 I updated my original post, and changed "Devices" to "Circuits" which is a very big difference. :p
 
Brimstone said:
The SPU is the new Power PC 300 series as that was reported as a rumor a while back on Apple Insider in December of 2003. This will replace the Power PC 400 series they sold off to Applied Micro Circuits.

Applied Micro Circuits Corporation announces definitive agreement to acquire intellectual property and a portfolio of PowerPC® 400 products from IBM, signs Power Architecture™ license

The PowerPC 300 series is what Sony and Toshiba got from the "CELL deal". Anytime they embed this into a product they probably don't have to pay a royalty to IBM. Something that I feel backs up this logic is when Sony Group licenses IBM Power Architecture-based chip technology was announced back in March. Toshiba hasn't done a similar deal because at this time they have no use for a general purpose processor, they're just going to embed the 350 into all sort of devices.

Toshiba announced that they will release products (an HDTV powered by a CELL based chipset) based on the CELL architecture and I think they are going to use the same PU's and APU's/SPU's PlayStation 3 will use.

If you're going to put a processor into a cellphone or HDTV, you not going to put something big and power hungry like a Power 4 along with some SPU's (Power 350's). Sony has to have the additional POWER license because they need it for Workstations and the Playstation 3.

I'm not saying this is fact, just the conslusion I come toafter reading all the press releases and rumors. Also I'm starting to believe Deadmeat is right about the clockspeed. The SPU is 1.15 Ghz, not the 4.6 Ghz. Thet 4.60 Ghz clock speed would be so far beyond any other competitor that it's just getting too hard to believe.

The SPU (in CELL related IBM literature and patent portfolio) would be the Synergistic Processing Unit, another name for the APU we have seen in the CELL patents which is as patents say a versatile "stream processor with 4-way SIMD engine".

This is not the PowerPC 300.

The PowerPC 300 might be related to the PU they used in CELL and in Xenon/Xbox 2's CPU (as the processor cores).

What IMHO PlayStation 3 and Xbox 2/Xenon have in common are the PU (or at least the XCPU 2 cores and the CELL's PUs are quite closely related).
 
Brimstone said:
That is an incredible clock speed. I don't think there is anything even remotely close to that speed in DSP's, CPU's, or whatever.

90 nm SOI manufacturing process + very optimized and relatively narrow stream processing unit = high clock-speed is possible.

Intel in 90nm will clock the ~470 mm^2 Itanium 2 (the 90 nm Montecito with 24+ MB of cache) at probably 2+ GHz and the ALUs in the 3.40 GHz Pentium 4 EE are running at 6.8 GHz, so I do not see the madness about running a 4-way SIMD engine (with logic shared between FP and FX resources and other bells and whistles, I do not want to over-simplify it too much), 128x128 bits regusters and 128 KB of SRAM (who has probably more than a 1 cycle load-use latency penalty) at over 4.0 GHz in 90 nm SOI technology.
 
Fox5 said:
one said:
Then, it's very natural they chose IBM as the first company which reached 1Ghz back in 1998.

What chip did they have that reached 1ghz(I'm guessing it wasn't powerpc as in the consumer market that reached 1ghz way after the athlon and pentium 3)? And more importantly how did it perform, and what was its power consumption and heat dissapation?

http://domino.research.ibm.com/comm/pr.nsf/pages/news.19980204_1000mhz.html

Well, it seems this Mr. Sang Dhong is the same researcher who appears in the forthcoming Cell presentation in ISSCC 2005. ;)

IBM demonstrates world's first 1000 MHz microprocessor

New technology to enable high-performance chips

Austin, Texas, February 4, 1998 - Engineers at IBM Research today said they have demonstrated the world's first experimental CMOS microprocessor that can operate at one billion cycles per second (1000 MHz or 1 GHz). Today's fastest processors typically operate at speeds less than 300 MHz.

The processor was designed at IBM's Austin Research Lab, which was established in 1995 to focus on advanced circuit design, as well as new design techniques and tools for high performance microprocessors.

"With this demonstration, we believe it is possible to design 1000 MHz products," said Mark Dean, IBM Fellow and director of the Austin Research Lab. "Equally significant is the fact that we've developed the tools and insight that will be necessary to push this technology to even greater performance levels."

Designed by a highly focused team of 15 engineers, the processor achieves clock speeds of up to 1100 MHz. The 1000 MHz chip contains one million transistors and was developed using IBM's existing 0.25-micron CMOS 6X technology. The microarchitecture, circuits and testing techniques resulting from this project will eventually be applied to microprocessors using IBM's recently introduced CMOS 7S "copper chip" technology.

Novel Architecture and Circuit Design
"Circuit and architecture innovations, including the merging of some functions and performing others in parallel, enabled us to reach the 1000 MHz milestone quickly and efficiently," said Sang Dhong, the Austin-based IBM engineer who led the development effort.

Among the team's achievements were:

* A multifunctional unit, which combines addition and rotation operations into a single circuit, and an innovative cache design, that combines the address calculation with the array access function.
* A dynamic circuit approach that greatly reduced the number of stages through which signals must propagate.
* Innovative clocking methods that further reduce the chip's cycle time and overcome the challenge of generating and distributing a timing signal -- or clock -- with a high degree of precision.
* A new testing technique that enables the tester to operate at a fraction of the speed of the processor core.
* The 1000 MHz chips were fabricated at IBM's Advanced Semiconductor Technology Center in East Fishkill, NY and tested at the T.J. Watson Research Center in Yorktown Heights, NY.

A paper detailing the achievement will be presented February 6 at the annual IEEE International Solid State Circuit Conference in San Francisco. IBM is also presenting two related microprocessor papers at the conference. One describes a commercial multi-threaded RISC processor demonstrating IBM's ability to use innovative microarchitecture technology in a commercial application. The other describes IBM's first use of copper technology on a product level design with the PowerPC 750 microprocessor.

IBM Research is staffed by approximately 2,800 researchers working at laboratories in the United States, Switzerland, Japan, Israel and China. Major areas of research include computer systems, applications and solutions, systems technology, physical sciences, mathematical sciences, storage and communications.
 
Brimstone said:
That is an incredible clock speed. I don't think there is anything even remotely close to that speed in DSP's, CPU's, or whatever.
I just asked that. Refer to the thread 'About some info from XB2 leaked documents'.
 
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