AMD RyZen CPU Architecture for 2017

[BRiT]

They did complain generally about the fact that the internet had the scans posted all over it here : http://www.cpchardware.com/cpc-hardware-n31-precisions-elucubrations/

Google Translation of the relevant paragraph for other's quick read:

At the time of the closure (early December), we had discussed a possible communication strategy around this new issue. Dandu suggested putting the famous benchmarks and a brief commentary in French and English on the day of release. For my part, I thought that a delay of 3-4 days was necessary, so that our subscribers and readers of the first hour retain exclusivity. In any case, we obviously knew that the tests would circulate quickly on the forums and that the websites would comment on them. But maybe not as fast and in this way. Just a few hours after the official release of the magazine on December 23, a user of the forum overclock.net has decided to post - of course without our agreement - a scan of the page in question. This one then spread quickly from forum in forum until making the "one" of sites like wccftech . More embarrassing to our eyes: some French sites have also reproduced in extenso the page in question, in disregard of the most basic ethical rules. If we do not see any problem with our colleagues doing their own analysis on the basis of our results, it is rather unpleasant to see his own texts copied / pasted shamelessly. The right to quote does not in any way legitimize the full resumption of an entire page. Among the journalistic pearls noted by the occasion are a colleague who says "Reddit" and another who considers that after having "broken" an NDA, it becomes " complicated to give lessons ". But enough whining, let's talk about it, precisely, of the NDA.

 

[fehu]

Their greedy malpractices ruined our greedy malpractices! That's not fair!

 

[Alexko]

What greedy malpractices were there on CPC's part?

In any case, the page linked above includes a scan of the magazine, published by CPC themselves, so it's all good.

 

[xEx]

in Gamer nexus KB review he said that they will have Zen bechs after CES(I could misinterpret what he said tho. Take your own conclusions.)

t=18m39s

Also rumors about the 8C max OC(usable) will be 4.4GHz and that the platform(mobos and cpus) will be very cheap.

https://www.reddit.com/r/Amd/comments/5lnxxu/ryzen_can_do_42_44_ghz_on_all_cores_buildzoid/

 

[Davros]

The above video says
the cpu's come in 4 different types
Y,U,H,S
then the website says
"with the i5 and i3 K-SKU CPUs"
so theres a K as well (I know K means unlocked)
then it says
"the cheapest i5 Kaby Lake CPU will be the i5-7400 (non-T),"
So theres a T and non T as well thats 7 types

from a b3d post

Kaby Lake models include a Core i5-7300HQ, i7-7700HQ and i7-7820HK.

So HQ's and HK's as well
its very confusing...
whats the difference ?

Personally I'd stay away from theses new cpu's If you have any usb 3.0 devices
the website printed block diagrams for the supporting chipsets and they only support the
new usa 3.0 standard

 

[hoom]

"USA USA USA"

I'll get my hat

Gen-Z(IEEE_802.3)

OOh I always assumed that one of the chip-internal standards would migrate out rather than Ethernet seep into the core of CPUs
Does this just make life easier for chip designers producing ever more complicated SoCs or does it have memory heirarchy/abstraction layer reduction implications in the super computing world?

Edit: is there any sign of a Release Date yet?

 

[Lightman]

Release is SoonTM.
Leaks point out to some form of paper launch / pre-launch at or just after CES.

 

[xEx]

Release is SoonTM.
Leaks point out to some form of paper launch / pre-launch at or just after CES.

I think the time is/will be good since no one is impressed with KL(what a surprise) and now they will forget about intels and talk about amd

Enviado desde mi HTC One mediante Tapatalk

 

[xEx]

Btw I was thinking, will it be possible/worth implementing a "giant" branch predictor/prefetch? Im asking because I was thinking "well Zen core will be/should be pretty small since it was designed from scratch for the 14nm processes so it should be very dense. Then AMD will have a huge amount of utilize space(compare to Intels CPUs) so what would be the best use of that space?" And I was thinking maybe AMD uses that space to make a "giant" branch predictor/prefetch or "over size" other parts of the cpu. But I don't know if that would be even worth implementing or will just be a waste of space and thermal dissipation. Maybe AMD just make the smaller cpu possible(without sacrificing performance) to make the cpu as cheap as possible to try to effort good prices and still be profitable.

 

[3dilettante]

OOh I always assumed that one of the chip-internal standards would migrate out rather than Ethernet seep into the core of CPUs
Does this just make life easier for chip designers producing ever more complicated SoCs or does it have memory heirarchy/abstraction layer reduction implications in the super computing world?

It's the physical layer in particular that Gen-Z is interested in, given its widespread use and speed. For the purposes of an interconnect, the links save power by adjusting the signalling to match the shorter distances and lower noise/losses.
That's rather speculative on my part that this might be used by AMD in a server chip, perhaps in the future.

Btw I was thinking, will it be possible/worth implementing a "giant" branch predictor/prefetch? Im asking because I was thinking "well Zen core will be/should be pretty small since it was designed from scratch for the 14nm processes so it should be very dense. Then AMD will have a huge amount of utilize space(compare to Intels CPUs) so what would be the best use of that space?"

The leaked wafer shot seems to give much of the area of a core complex to the cache hierarchy and uncore, which is customary for high-performance chips and for CPUs with server aspirations in particular. I'm not sure I follow how Zen will have that much more space than Intel. Zen's 14nm is lags Intel's process if a number of metrics, such as its back end metal layers being from a slightly density-optimized 20nm node.
Zen is also a wider core than AMD's prior generation, except for its vector units. That might be matched by AMD's having 8 cores, and the overall chip might have prioritized having a smaller die.

And I was thinking maybe AMD uses that space to make a "giant" branch predictor/prefetch or "over size" other parts of the cpu.

The branch predictor should be improved, and hopefully generously resourced. However, since this is a 3-4 GHz+ core, everything also needs to be fast and power-efficient. Physical size can be a barrier to speed due to longer distances for signals to travel, and having more hardware can also mean having more power consumption.

 

[xEx]

It's the physical layer in particular that Gen-Z is interested in, given its widespread use and speed. For the purposes of an interconnect, the links save power by adjusting the signalling to match the shorter distances and lower noise/losses.
That's rather speculative on my part that this might be used by AMD in a server chip, perhaps in the future.


The leaked wafer shot seems to give much of the area of a core complex to the cache hierarchy and uncore, which is customary for high-performance chips and for CPUs with server aspirations in particular. I'm not sure I follow how Zen will have that much more space than Intel. Zen's 14nm is lags Intel's process if a number of metrics, such as its back end metal layers being from a slightly density-optimized 20nm node.
Zen is also a wider core than AMD's prior generation, except for its vector units. That might be matched by AMD's having 8 cores, and the overall chip might have prioritized having a smaller die.


The branch predictor should be improved, and hopefully generously resourced. However, since this is a 3-4 GHz+ core, everything also needs to be fast and power-efficient. Physical size can be a barrier to speed due to longer distances for signals to travel, and having more hardware can also mean having more power consumption.

I was talking about Intels CPU having 50% or more area dedicated to the GPU which AMD doesn't have so there is a huge difference between the 2 that can be utilize but yes adding parts have counter effects in thermals and more complex logic. I was just thinking that maybe AMD can use the difference in space for something.

 

[3dilettante]

I was talking about Intels CPU having 50% or more area dedicated to the GPU which AMD doesn't have so there is a huge difference between the 2 that can be utilize but yes adding parts have counter effects in thermals and more complex logic. I was just thinking that maybe AMD can use the difference in space for something.

Summit Ridge is the smallest non-APU being mentioned, so it's no GPU but with twice the CPU cores. There's a fair amount of on-die area between the clusters, probably a southbridge section, a security processor, and a decent amount of IO.

 

[xEx]

Well I was talking about CPUs with equal core count.

 

[3dilettante]

Well I was talking about CPUs with equal core count.

If that's the case, then the roadmap so far indicates AMD uses the spare die area in a quad-core for a GPU.

 

[xEx]

If that's the case, then the roadmap so far indicates AMD uses the spare die area in a quad-core for a GPU.

I dont remember seen the SR3 as a APU. which roadmap you're about?

 

[3dilettante]

My understanding is that the SR designation is for Summit Ridge, which is an 8-core die. If there's a reduced core count, it's a salvage die.

 

[xEx]

Rumors suggest that SR8 will be the 8core, SR5 the 6core and SR3 the 4core of the FX lineup which as for what we know wont have a GPU. If you have NDA info(in this forum you never know) then you can share I wont tell anyone I promise

 

[3dilettante]

Rumors suggest that SR8 will be the 8core, SR5 the 6core and SR3 the 4core of the FX lineup which as for what we know wont have a GPU. If you have NDA info(in this forum you never know) then you can share I wont tell anyone I promise

Zen works in a granularity of core complexes, which are 4 cores each. That seems to further reinforce that the lower tiers are salvage dies, although that there would be salvage was virtually guaranteed from the beginning.

 

[xEx]

Zen works in a granularity of core complexes, which are 4 cores each. That seems to further reinforce that the lower tiers are salvage dies, although that there would be salvage was virtually guaranteed from the beginning.

Yes Im sure there will be but I really doubt that the 4 cores will be all disabled versions of the 8 cores since the demand for the 4 core will be higher and producing only 8 core and selling them as 4 core would be extremely expensive.

 

[3dilettante]

The rumor articles I saw indicate that SR means Summit Ridge, which is specifically the name of an 8-core die and has "up to 8" as a product.
Raven Ridge is the first one listed as an "up to 4" core device, and is an APU.