Interestingly, Summit Ridge (the 8-core, big Ryzen) is actually an SoC. Beyond the dual DDR4-3200 controllers, it features 8 SATA 3.0 links, three USB 3.0 links, four (yes, the article says four) Ethernet links, HDA support, etc. There are also two PCIE 3.0 controllers with 16 lanes each. Of those 32 lanes, 8 are dedicated to internal communication between all the IP blocks, while the remaining 24 can be used externally: 16 for graphics, 4 for external storage (NVMe, SATA Express) and 4 to connect to a southbridge. Obviously, the latter isn't strictly necessary and entirely optional.
It's curious that the controllers lose 8 lanes to internal communication. The southbridge complex itself seems to be modularized, but I feel like the bandwidth offered indicates it's not part of the main data fabric.
Earlier in the thread, I tried to reconcile some of the slides and rumors surrounding Summit Ridge, the HPC APU, and the server variants.
One of the items was trying to make sense of the claim that the HPC APU (using Zeppelin) was going to have 64 lanes of PCIe while at the same time being able to interface with 4 GMI links.
The guess at the time was that GMI was overlaid on the PCIe links, but if Zeppelin is 2x Summit Ridge the above information would contradict Zeppelin needing more than 32 lanes per chip to have anything left over to connect to the GPU.
Since then, Gen-Z was announced, and it uses Ethernet (IEEE_802.3) for its physical layer. It's not coherent, but is agnostic to coherence primitives being passed through it. That might free up the PCIe lanes, although it's still not a full match since Summit Ridge is reserving links for some reason and some of the disk IO doesn't add up.
This might give an idea as to why AMD is showing up in OpenCAPI (PCIe), CCIX(PCIe), and Gen-Z(IEEE_802.3).
That doesn't rule out Zeppelin not being a straightforward doubling of Suumit Ridge, or possibly a more flexible link strategy where lane reservations change or can be augmented based on GMI, an MCM, or a GPU being linked. (ed: For example, if GMI goes over Ethernet this might allow a Vega GPU's own 16x PCIe link to be used externally. This implies a Vega variant with a significant amount of network communication capability if there's a standalone version.)
Motherboard manufacturers, however, might not be thrilled about this, but at this point it's hardly a surprise.
If there's a cost reduction of some kind, it might encourage some board makers to not sideline AMD as much, or at least leave them fewer corners to cut.
However, that would depend on the quality of the IP AMD has integrated. AMD has some partnerships for southbridge IP that raised some questions as to overall competitiveness. I'm not sure where its current and prior generation CPU memory controllers were sourced, but they haven't impressed either.
