AMD RyZen CPU Architecture for 2017

Is this 4 Summit Ridge chips or something different?
The claim is that Summit Ridge has 32 lanes per-die, and 8 of them are unavailable off-die.
That's 1.5 16-lane links.
The die itself can have more 16-lane links than the consumer product line Summit Ridge. So what I said was that the die would possibly have 4+ 16-lane links which let it scale from 1-chip package as Summit Ridge, to 4-chip package as Naples. Of course, another view to this is counting GMI links separately from these PCIe links.

There are rumors that Naples has 128 external links, and making them fully connected means there's a negative number of links available to the outside world. Something would need to be invalidated since Summit Ridge provides no room for external connectivity if PCIe is 24 external links per chip.
It is possible if each die has five links. Then for a quad-die Naples, 3 per die would be used for on-package connection, while 2 per die would be available for external connection. This would put it at 128 lanes as rumoured.

The two dividable 4-lane links, that is set for NVMe/SATA/GPP/FCH in the Summit Ridge AM4 platform, are probably derived from one of these.

Since the HPC APU is supposedly using Zeppelin, does it have more than 2x the claimed link count of Summit Ridge?

There's still a mathematical pathway to getting 64 links of external connectivity with a 2x Summit Ridge scenario, even if that's only 48 lanes available externally from the CPUs, but only if via some coherent magic a Vega GPU's own 16x PCIe link can be used.
For the cancelled G2012/C2012 platform, AMD was (on the record) having configurable links that support ccHT and PCIe. PCIe Gen 3 supports multiplexing too.

5 links would satisfy the constraints of (1) 4 16-lane links from the two dies to Vega; (2) 4 16-lane PCIe links going out; and (3) a possible 16-core Naples socket that has half the I/O and memory channels than the 32-core one. But it would leave the inter-CPU connection with just one 16-lane link, but it could be compensated by a higher SerDes speed though (as it being on package).

An interesting note is that the G2012/C2012 platform was planned to have five 16-lane links: 2 ccHT links, 2 ccHT/PCIe links and 1 PCIe link. The diagram can still be found in the Family 15h SOG.
 
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But it would leave the inter-CPU connection with just one 16-lane link, but it could be compensated by a higher SerDes speed though (as it being on package).
Note: In theory, the traffic can be routed through the Vega GPU if the one and only link between the CPU dies is congested.

An interesting note is that the G2012/C2012 platform was planned to have five 16-lane links: 2 ccHT links, 2 ccHT/PCIe links and 1 PCIe link. The diagram can still be found in the Family 15h SOG.
I am not quite sure if I remembered the number of configurable links correctly. So correct me if I am wrong.
 
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Interesting! More interesting still is whether the chip can, when some cores are idle, Turbo up to 4GHz or a bit more without blowing through its TDP.
 
Even if that'd only 2 cores @5ghz on air that's certainly very good signs of OC potential.
 
Those guys...

"The I / O multiplier is not clamped at this time and is configured in steps of 0.25x" So AMD manage to get .25 milti steps. that should allowed for higher OC or more precisely more close to the chips limits.

"Other Ryzen ES are currently in the hands of overclockers" So these are ES and not finish products. If these are ES and with the low AMD's resources im assuming they are focus in one chip at time this means its the 8C variant. If this is true the finish 4C would be a beast in frequency.

"and you should not delay to learn more: a demonstration of overclocking could occur at the CES if good results are achieved." So there will be a Zen presentation at CES and even maybe (mostly likely) an OC potential announcements.
 
*AHEM* This site still has rules against directly posting scans of copyrighted material or linking directly to scanned copyrighted material. Please stop breaking the rules.
 
I understand why I can't inline copyrighted images, but if I can't even link to a website that hosts such images then how can I bring that content to the attention of this forum's users?
 
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I understand why I can't inline copyrighted images, but if I can't even link to a website that hosts such images then how can I bring that content to the attention of this forum's users?

You'll have to wait until legal means are available.
 
I understand why I can't inline copyrighted images, but if I can't even link to a website that hosts such images then how can I bring that content to the attention of this forum's users?

It might be technically legal to merely provide a link, but it's hard to assume that too - law and jurisprudence evolve, some torrent farms get closed down although I believe you can make one that would be "technically legal", ignoring possible recent laws.
I can also link to tentacle rape, but I don't think it will be well received.
 
In my original post about Canard PC's Ryzen benchmarks I inlined images and linked to a website that hosted those images, and yet only the inlined images were deleted while the link was not. Why is linking to copyrighted images hosted by overclock.net different from linking to similar images hosted by imgur.com?

Your original link was to another site which had content. Your recent link was directly to an image hosting site that has no other content. At the time it was a subtle distinction and a judgement call. Looking back the original post should have been completely removed too. The situation has now been corrected.
 
Was this site notified that the images were copyrighted by the copyright holder? Or was this a judgement call?
 
Was this site notified that the images were copyrighted by the copyright holder? Or was this a judgement call?

It was obvious they were scanned from a print magazine.
 
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