The die itself can have more 16-lane links than the consumer product line Summit Ridge. So what I said was that the die would possibly have 4+ 16-lane links which let it scale from 1-chip package as Summit Ridge, to 4-chip package as Naples. Of course, another view to this is counting GMI links separately from these PCIe links.Is this 4 Summit Ridge chips or something different?
The claim is that Summit Ridge has 32 lanes per-die, and 8 of them are unavailable off-die.
That's 1.5 16-lane links.
It is possible if each die has five links. Then for a quad-die Naples, 3 per die would be used for on-package connection, while 2 per die would be available for external connection. This would put it at 128 lanes as rumoured.There are rumors that Naples has 128 external links, and making them fully connected means there's a negative number of links available to the outside world. Something would need to be invalidated since Summit Ridge provides no room for external connectivity if PCIe is 24 external links per chip.
The two dividable 4-lane links, that is set for NVMe/SATA/GPP/FCH in the Summit Ridge AM4 platform, are probably derived from one of these.
For the cancelled G2012/C2012 platform, AMD was (on the record) having configurable links that support ccHT and PCIe. PCIe Gen 3 supports multiplexing too.Since the HPC APU is supposedly using Zeppelin, does it have more than 2x the claimed link count of Summit Ridge?
There's still a mathematical pathway to getting 64 links of external connectivity with a 2x Summit Ridge scenario, even if that's only 48 lanes available externally from the CPUs, but only if via some coherent magic a Vega GPU's own 16x PCIe link can be used.
5 links would satisfy the constraints of (1) 4 16-lane links from the two dies to Vega; (2) 4 16-lane PCIe links going out; and (3) a possible 16-core Naples socket that has half the I/O and memory channels than the 32-core one. But it would leave the inter-CPU connection with just one 16-lane link, but it could be compensated by a higher SerDes speed though (as it being on package).
An interesting note is that the G2012/C2012 platform was planned to have five 16-lane links: 2 ccHT links, 2 ccHT/PCIe links and 1 PCIe link. The diagram can still be found in the Family 15h SOG.
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