AMD informed der8auer that only 2 dies are working. Else this would be 8 channel 128 lanes etc.
AMD informed der8auer that only 2 dies are working. Else this would be 8 channel 128 lanes etc.
Anarchist4000
Veteran
Or they found a way to use a die with no good cores, simply to extend the fabric in this case. Epyc and Ryzen should be the same chip with some packaging changes.
Now to hope a pencil mod unlocks the other half!
If all the Threadripper products are like that, it would seem that it could not use more than one GMI link per core pairing. Bandwidth-wise, it would have mostly removed bottlenecking relative to a true quad-channel die.
Latency would still be hit, but on the other hand given the presence of unimpressive inter-CCX latency on-die, the hit measured for EPYC seemed like a survivable one at the one-hop stage. It would be more prohibitive in terms of latency variation if the unused dies somehow participated in the fabric.
At least the snoop filters in the dual-die case should be generous enough to cover everything in cache.
Latency would still be hit, but on the other hand given the presence of unimpressive inter-CCX latency on-die, the hit measured for EPYC seemed like a survivable one at the one-hop stage. It would be more prohibitive in terms of latency variation if the unused dies somehow participated in the fabric.
At least the snoop filters in the dual-die case should be generous enough to cover everything in cache.
All the material shown by AMD in the past indicated it's 2x8 core dies.
Edit: and as stated AMD confirmed 2 dies active.
Since all X399 boards have half of the memory channels (and PCIe lanes) wired to the same "half" of the socket (for compatibility), that would mean TR will always have the same pair of dice disabled.
This begs the question, does AMD really disables the "unwired" pair or it just goes unpowered and what will happen if a TR is plugged in a server SR3 socket board?
This begs the question, does AMD really disables the "unwired" pair or it just goes unpowered and what will happen if a TR is plugged in a server SR3 socket board?
Anarchist4000
Veteran
They aren't throwing them away, but likely only using the memory controllers and fabric resources for IO. Threadripper is a quad channel platform unlike the Ryzens.
Also the possibility they replace two dies with other chips having a similar footprint. Say Vega11 if the Infinity footprint was identical.
If it were the case that Threadripper could use the controllers and IO of an otherwise dead die, there probably could have been an EPYC SKU with one core and 8 channels of memory. AMD left at least one CCX active per die in its lowest core count product (ed: correction, one active per CCX, with two active per die).
It might be part of the design or a quirk similar to how it seems the number of core inactivations have to be symmetric across a die.
One possible reason may be the need for there to be an active core on-die to handle system or platform exceptions. A data probe, coherent slave, PHY, or fabric error on a remote die could be experiencing a problem with remote communications, and so might not be able to reach a remote CCX's CPU to detect or handle the error.
It might be part of the design or a quirk similar to how it seems the number of core inactivations have to be symmetric across a die.
One possible reason may be the need for there to be an active core on-die to handle system or platform exceptions. A data probe, coherent slave, PHY, or fabric error on a remote die could be experiencing a problem with remote communications, and so might not be able to reach a remote CCX's CPU to detect or handle the error.
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Anarchist4000
Veteran
Didn't Epyc still have the cache with the single cores? While a single core Epyc may be possible, they may have felt it wasn't warranted. I'm not sure the blanks are doing anything beyond having a programmable controller parse packets and forwarding them. So far it seems the only bad die is the one where Infinity doesn't function.
I erred in stating single core, the minimum would likely be an 8-channel package with one die with two single-core CCXs, if the CCXs could remotely connect and manage the elements on the other dies.
The specific optimization space is some form of DRAM-limited workload with per-core licensing. Keeping the DRAM and IO, and quartering the licensing costs seems like it might be a possible target given how much it reduced counts with the 7251.
Even if those other dies were mostly just forwarding packets, a simple controller isn't necessarily able or permitted to handle a system error raised on the link it has back to the CPU on the other side.
hoom
Veteran
Or there is a high fail rate in making the MCM.
Or its just an ES & normal ones will be 2-die.
Maybe there will be both dedicated 2-die & salvage 4-die?
Per a followup by Anandtech, it was an engineering sample and may mean the final product will not be housing four full dies.
This does relax the need for a mechanism to access the memory controllers and IO that are physically tied to specific points of the MCM, if those are the bad dies. As an engineering sample, it's more of a matter of just needing enough MCMs out there that don't fail at those critical points and those that cannot match that pattern are discarded anyway.
If that diagonal pattern for the routing of the DDR4 interface holds for a dual-die Threadripper, however, that might pose complications for any postulated Threadripper+GPU MCM, since that doesn't leave a conveniently contiguous spare area. A half-EPYC MCM might, however.
This does relax the need for a mechanism to access the memory controllers and IO that are physically tied to specific points of the MCM, if those are the bad dies. As an engineering sample, it's more of a matter of just needing enough MCMs out there that don't fail at those critical points and those that cannot match that pattern are discarded anyway.
If that diagonal pattern for the routing of the DDR4 interface holds for a dual-die Threadripper, however, that might pose complications for any postulated Threadripper+GPU MCM, since that doesn't leave a conveniently contiguous spare area. A half-EPYC MCM might, however.
D
Deleted member 13524
Guest
This is good because it sounded like the hell of a waste of silicon.
Maybe AMD developed the 4-die MCM frst so they could release Epyc and Threadripper at the same time, and then they'll start putting out 2-die MCMs for the last model.
AMD could still offer some quad-die Epyc SKUs as TR in the future, if there's enough salvaged server parts and market demand for TR.
Only way you would need to use "salvage part" as TR instead of Epyc would be completely broken memory controllers or some such - Epyc models go down to 1 core per CCX enabled after all
Anarchist4000
Veteran
Possibly, but maybe there is a small controller present that can? Something used for their transparent encryption outside the cores. I'm hesitant to limit that capability to only CPUs because I have a hunch Ryzen and Vega dies are somewhat interchangeable with Infinity. Each chip creates the same SERDES links, but features different memory controllers.
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