AMD RyZen CPU Architecture for 2017

kalelovil said:
The memory controller is said to be (IIRC by The Stilt) very similar to the one in previous generation's Carrizo/Bristol Ridge. It is supposedly based on Synopsys off-the-shelf IP.
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I recall seeing this being disputed, but I wouldn't know where to find the victor with the information available on the web.
Some of the data being cited for this included the same or nearly same system interfaces for the hardware, but keeping BIOS or firmware-level abstractions stable may play into that.
I think there were other counter-claims regarding LinkedIn profiles and other inferences being drawn.
 
Malo said:
Yeah it makes me want to go buy an AIO cooler and samsung b-die memory..... maybe one day soon.
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Yeah it's great to see the real performance of the chip coming into daylight. Unfortunately the masses still have performance of day one printed in their minds. This is the drawback when your performance isn't top notch at day 1.
 
Clukos - great job on all these tests!
I can only confirm, that what you see, I also noticed on my setup few weeks ago, when playing with tight sub-timings and my B-die memories. I've copied 2133 Auto timings and ran them at 3200, which offered measurable performance uplift to DOCP 3200 setting. Some tests were showing double digit gains!
I'm glad you found time to investigate it properly and draw these pretty graphs :)
Hats off to you!
 
Dygaza said:
Yeah it's great to see the real performance of the chip coming into daylight. Unfortunately the masses still have performance of day one printed in their minds. This is the drawback when your performance isn't top notch at day 1.
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I would say that even if it were launched now after the latest firmware and all the research put into tweaking latencies, many of the improvements would be outside the scope of the masses. Hunting down B-die Samsung modules, researching recommended manual BIOS tweaks, and then figuring out whether or not the actual hardware you have is able to reliably sustain custom settings is not something the mass market will ever do.

I think it's a fair judgement of a product overall if putting that much on the buyer with no guarantee of success is a negative. If there is a microarchitecture that doesn't need that amount of work to achieve equal or better performance, it is fine to give it bonus points in my opinion.
 
Dygaza said:
Yeah it's great to see the real performance of the chip coming into daylight. Unfortunately the masses still have performance of day one printed in their minds. This is the drawback when your performance isn't top notch at day 1.
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IMHO, it was still a better window for AMD to launch their chips before the new 7000 series HEDT i7/i9 chips. 499$ 3.6 GHz 8-core Ryzen flagship was compared against the 1089$ 3.2 GHz 8-core 6900K and the 1723$ 3.0 GHz 10-core 6950K and fared very well in those comparisons. People were truly impressed about the perf/$. Now Intel has 10-core 7000-series chip at 999$ and 8-core chip at 599$ (40% price drops). Intel HEDT clock rates have also been improved by 300/400 MHz. Delaying Ryzen by 6 months could have also meant delays for Threadripper and EPYC. Intel had to rush their HEDT to market very quickly to combat Threadripper, and has had various problems. Bad press for Intel is good press for AMD. If AMD can keep their Threadripper launch schedule, it will be benchmarked against Inte's top of the line 10-core and 12-core chips instead of their forthcoming 16-core and 18-core offerings. We all know that Threadripper will crush 10/12 core chips in highly threaded tasks. AMD can't afford delays as Intel is stepping up their game.

EPYC launch could have also been better if it happened 3 months ago. Intel got their newest chips ready just in time. AMD marketing slides were still comparing EPYC to Intel's current gen, but Intel refreshed all their chips at EPYC launch date. Intel will also launch Coffee Lake later this year. It will feature 6-core consumer processors (non-HEDT) and i3 will step up to 4-cores. Also 10nm Cannonlake was planned to be launched at late 2016, but was delayed by a year. If Ryzen would have been delayed 6 months and these Intel chips would have been on time, it could have been a much less impactful launch for AMD. I think AMD played their cards right. None of these small issues were game changers. Press still loved the CPU.
 
I agree with the timing that it was right. What can be questioned afterwards, could AMD have placed more resources into working with motherboard vendors earlier to get things sorted out. Did they in their own internal testings even realised how much memory bandwidth and latency helped the chip outside of the standard JEDEC timings? Assuming they did, doesn't automatically mean they did.
 
These are Corsair 3200Mhz 16-18-18-18-36 single rank sticks, 2x8GB (CMK16GX4M2B3200C16). Im running them at 1.365V as suggested by the Stilt. Soc Voltage is 1.05. I'm having less luck with the CPU, which requires big amounts of voltage even at 3.85Ghz.

The Stilt suggested even tighter timings on the Finnish Io-tech-forums which I haven't tried, yet. See attachment.

yekMO6E.png
 
There's something wrong with Ryzen + Windows 10 CU + Dx11. Take a look at the same test (API overhead) with a clean install of Windows 7: http://www.3dmark.com/3dm/21222445

That is a ridiculous difference which is reflected on anything using Dx11. Dx9, Dx10 are mostly the same, or slightly higher. I'm not sure what's happening here, I'll test Vulkan as well.

Edit: Vulkan is actually slightly lower: http://www.3dmark.com/3dm/21223226

So the problem seems to be isolated to Dx11 only.
 
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Arghhh, I was just about to post it. :p

Well, to spoil the video, the sample he sacrifices has all the four dies under the hood, just like Epyc. Weird.
 
Weird. Surely it would be cheaper to produce a separate configuration in the same package with only 2 dies rather than a single package with 2 wasted dies? Or are these 8-core dies simply that cheap for them to produce they can literally throw them away in these TR designs? Is this some kind of salvage EPYC where 1 or 2 dies are killed in the process of making a full EPYC?
 
If the TR line is just binned Epyc SKUs, then the wafer yields must be indeed through the roof, so AMD just won't bother with dedicated two-die SKU.
 
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