AMD RyZen CPU Architecture for 2017

Malo why did amd want it taken down ?
I don't know, apparently der8auer doesn't either. It's likely that because it was an engineering sample and possibly not representative of the final product (as Ian Cutress alluded to) that it provided incorrect information regarding Threadripper.
 
Memory and peripheral I/O wiring for TR/Epyc(?)

AghcVZM.png

Beautiful.
 
Possibly, but maybe there is a small controller present that can? Something used for their transparent encryption outside the cores. I'm hesitant to limit that capability to only CPUs because I have a hunch Ryzen and Vega dies are somewhat interchangeable with Infinity. Each chip creates the same SERDES links, but features different memory controllers.

Possibly, although as a slave device there would be classes of issues where Vega would defer to a CPU.
What some of the exception or fault handling would do if data within an encrypted VM was associated with an error that propagated up to the hypervisor is uncertain. It would seemingly constrain some of the tools used to allow systems to manage failures or log data, unless those became a vector for leaking data.
Involving the secure enclave in link errors and calling interrupt/exception code might itself become a vector via bus-glitching or some kind of malicious remote node.
 
That 4 die Threadripper is such a wind up. I was planning on buying 1950X this autumn. Now I'm wondering if there'll be a 32-core Threadripper. 1999X for Christmas?
 
There will is there is a market for it and as long as AMD don't think it will cannibalize much of Epyc sells.
 
That 4 die Threadripper is such a wind up. I was planning on buying 1950X this autumn. Now I'm wondering if there'll be a 32-core Threadripper. 1999X for Christmas?
That would scale horribly on just four mem channels.
I wonder how much more would a X399 motherboard cost with fully wired SR3 socket.
 
That's Gubbi's point.

As far as I can tell the sockets for EPYC and Threadripper are only marginally different. So wiring up and fitting the memory on a consumer mobo is the real question, I suppose. You end up with a server mobo and server processor. So why even make consumer 32 core Threadripper and mobo...
 
I don't know, apparently der8auer doesn't either. It's likely that because it was an engineering sample and possibly not representative of the final product (as Ian Cutress alluded to) that it provided incorrect information regarding Threadripper.
He is quite sure that the information pertained therein still is legit. Maybe they want to do yet another double blind test. Like - can you feel the difference in L3 latency...
 
As far as I can tell the sockets for EPYC and Threadripper are only marginally different. So wiring up and fitting the memory on a consumer mobo is the real question, I suppose. You end up with a server mobo and server processor. So why even make consumer 32 core Threadripper and mobo...
Might make sense if the pins were re-purposed for power delivery. Save costs from 4 fewer memory channels, but leave open the possibility of other accelerators with integrated memory: FPGAs, DSPs, GPUs, stacked DRAM, etc. That would follow their heterogeneous capabilities when Epyc with 128 PCIE lanes was overkill. Threadripper ITX platform, with a dozen USB3.1 ports, Thunderbolt, dual 10GbE networks, etc that wouldn't be excessive at all.
 
Can I make an semi-oftipic question?

How ryzen 3 1200 compare against an old i5 4590?

Enviado desde mi 2PS64 mediante Tapatalk
 
Back
Top