Clearly not, if the published data is correct. Somewhere between 6800 and 6800X seems possible.
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Bondrewd
Veteran
It'll be kinda game-dependent.
When exactly was the last time AMD being *not* the second-best?
I guess they managed to stay on top with Hawaii for some time in 2013. Since then it was the horrible GCN stagnation (4GB Fury, no highend with Polaris, hyped Vega 64, sad Vega VII) and two pretty solid RDNA gens.
In single games it might reach a 6900XT, especially in RT. In a bigger parcour as Hardwareunboxed, it will land below a 6800XT, if not clocked much higher than 3ghz.
TESKATLIPOKA
Newcomer
So in some games It will be on the level of RX 6900(6950)XT and in others higher than RX 6800?
RX 6950XT is 34% faster than RX 6800.
Is this even at 1080p? Then N33 is not as good as I thought based on your earlier posts.
Bondrewd
Veteran
Yeah, gotta wait out and see.
The mobile variant (think 7800S) is hnnnnmnmnmmng tho.
Welcome to the "whole new uArch" deal.
Navi 33 with its 4096 stream-processors at ~3 GHz Game Clock should reach 24,6 TFLOPS, while Navi 21 / Radeon RX 6900 XT with 5120 stream-processors at 2015 MHz gets 20,6 TFLOPS. That's like ~20 % higher arithmetic performance. It's hard to imagine Navi 33 will be significantly slower than Navi 21 until RDNA 3 e.g. halves the ALU:TEX ratio (like Nvidia did with Ampere) or reduces the ALU:ROP ratio significantly.
And that with 1/3 of the die. Seriously, do you people really believe that? That would be the first time in history that a company can increase compute throughput by 2.5x ( i guess AMD needs ~50% more transistor) while reducing the die size by 20% over the previous generation on a slighty better node.
nVidia doubled FP32 compute throughput only from Turing to Ampere but they used (inclusive every other improvements) 30% more transistors and a shrink von 12nm to 8nm (full node step).
nVidia doubled FP32 compute throughput only from Turing to Ampere but they used (inclusive every other improvements) 30% more transistors and a shrink von 12nm to 8nm (full node step).
Bondrewd
Veteran
No one told you AMD engineering was sane.
Hence why I've been shilling those parts for almost a year now, maybe more.
They're positively nuts.
Jawed
Legend
Yep a bitter lesson from history. A 384-bit version with 16 CUs would simply have trashed GTX 280 and still would have been radically smaller (though about the same power consumption).
The whole idea that Crossfire (x2 card) was viable as a flagship card
It depends on where you spend the transistors. It wouldn’t be the first time AMD designed an architecture targeting high flops on paper. RDNA is actually very balanced though aside from RT so I would be surprised if they starting chasing unusable flops again for their gaming arch.
Feeling major deja vu from the Navi3x hype. It’s almost like we heard the exact same promises for Navi2x from the same source.
DegustatoR
Legend
I mean with Nvidia pushing >30 Tflops in the same area as Navi 21 it is rather imperative for AMD to improve their FP32 flops/die area if they don't want to start falling behind again with shaders becoming more and more math heavy.
That being said though Nvidia will likely be pushing ~40 Tflops from the same area in Lovelace so improving that by 2-2.5x won't lead to an AMD advantage in this metric still.
And yeah, with WGP rebalancing we can probably forget about RDNA3 scaling anywhere near linear along flops changes in comparison to RDNA2.
That being said though Nvidia will likely be pushing ~40 Tflops from the same area in Lovelace so improving that by 2-2.5x won't lead to an AMD advantage in this metric still.
And yeah, with WGP rebalancing we can probably forget about RDNA3 scaling anywhere near linear along flops changes in comparison to RDNA2.
Bondrewd
Veteran
So far it's causing confusion and not hype but whatever.
Would it be?
R520 (Radeon X1800 XT) ⇾ R580 (Radeon X1950 XTX) was 3.25× with just 22 % more die space (including other improvements, e.g. beefier ROPs) on the same node and using the same architecture.
R520 (Radeon X1800 XT) ⇾ RV570 (Radeon X1950 PRO) was 2.16× with 20 % less die space on a half-node step (inferior 80nm process which resulted in reduced clock speed). With a clock increase comparable to Navi 21 ⇾ Navi 33, it would be 3.38× higher arithmetic performance at 20 % smaller area - much bigger step than Navi 21 ⇾ Navi 33 (achieved even on the same architecture).
RV670 (Radeon HD 3870) ⇾ RV770 (Radeon HD 4870) was 2.41× with 33 % more die space (including much improved ROPs) on the same node, done within 7 months.
Don't forget that Navi 21 ⇾ Navi 33 (maybe increases arithmetic performance, but) reduces Infinity Cache by a factor of 4. Bus-with is reduced by a factor of 2. There were hints about simplified ROPs (some ops could be moved to ALUs) etc.
Jawed
Legend
It's worse than that, I reckon, since RT explicitly relies upon math throughput in AMD's design (assumption based upon there being no sight of a re-design for RT in patent documents). So Navi 31 merely catches up to where it should have been in Navi 21 from day one...
... while NVidia will be leaping far ahead again, it seems.
As far as I understand it with two SIMDs sharing a register file it's guaranteed to scale worse than RDNA 2 because any 3-operand instruction in one SIMD is going to interfere with the throughput of the other SIMD, even if only momentarily. Despite all the possible compiler jiggery-pokery we've seen in open source patches, we also know from history that relying upon the compiler is the best way to trash throughput.
AMD has Navi24 on 6nm with 64bit, 16mb L3 cache, 1024SP, 100mm^2, 50 bxtors/mm^2 and high clocks (2900GHz?!) at 105W TDP.
We are talking about an archivement on the same process which laps anything TSMC was able to provide with their processes since years. For example Apple has only improved efficiency by 20% with M2 GPU over M1.
Bondrewd
Veteran
But that's exactly what they're doing, if the data is right. 4096 Shaders in a smaller size chip than 2048 is only possible, if you cut other corners. Just cutting out the Re-Order Buffer isn't enough by far. It's impossible to double the TMU count in such a small chip. TMUs aren't small. Therefore the ALU:Tex ratio must be halved. Same should apply for ROPs. They are going from 237 mm² to 203mm², the transistor count might stay the same, if they go for higher density, but not much more.
TESKATLIPOKA posted the most probable configuration already:
Only the shaders will be doubled compared to N23. The other stuff will stay the same.
I'm waiting for the qoute in the angstronomics article, where he's writing about TMU counts or ROP counts?
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