Subtlesnake
Regular
Well if they managed to fit 33% more CUs in the same power envelope, the power savings had to come from somewhere. We should compare the 12 CU Strix Point with Phoenix at the same TDP.
Leoneazzurro5
Regular
Well it's difficult to say if it's fixed or not, in a mobile part you are power and thermally limited but if we see a +33% more CU at same power with a slight frequency bump that could mean that we could see an improvement on higher powered parts as well, unfortunately we will never know that because it seems no RDNA3.5 desktop parts are coming.
Like going from N5 to N4....
33% sounds like a lot here, but we're talking fairly small CU counts still. It's not gonna take a lot more to feed them.
So yea, hard to say for sure.
DegustatoR
Legend
Let's wait for benchmarks before judging perf/watt changes shall we? It's not like 7900X is always at its 170W power limit in actual applications, same goes for 7800X. Just setting 9000 parts TDPs lower doesn't mean that perf/watt will improve much.
Leoneazzurro5
Regular
Phoenix was already on N4.
And even if we take additional improvements of N4P and DTCO, the power savings are in the range of 5-10% at best (At iso clock/performance). Strix point is probably memory bandwidth limited as well.
As for the 2.9GHz clock - it tells absolutely nothing. These values are “up-to”, not real world clocks. The 2.8GHz iGPU in Phoenix runs at 1.4GHz in some form factors under certain workloads, so these ~3GHz numbers are more or less marketing values. No technological conclusions can be drawn from them.
Ah that does change things.
Supposedly it was planned with 16MB Infinity cache at one point in its design phase but it was dropped later due to cost reasons. Would certainly have helped both power/performance and been more useful than the NPU for most consumers. Phoenix had just 2 MB L2, Strix Point should have at least 4 MB I would think (Intel has gone to 8 MB with Lunar Lake).
And Strix Halo has 32 MB Infinity cache as per rumoured specs.
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actually it telling a lot, as the messenger promised 500 - 600 Mhz clock increase over RDNA3
Subtlesnake
Regular
500 MHz seems quite optimistic, but I would expect to see a clock speed increase at the TDP ranges these chips are operating at, all things being equal (12 CU vs 12 CU).
Not really, you cannot say anything from "up to" specs between different generations. Unless we see an apples to apples comparison, say a 12CU vs 12CU in a GPU bound workload in the same exact chassis and TDP. Even then there will be some differences due to CPU but you would at least see if the GPU clocks are meaningfully higher.
Actually in typical thin and light laptops which are configured to run sub 30W, there might not be enough power headroom for either to hit their max clocks. A chassis with a 50W+ power limit CPU might actually have enough headroom but those usually come with dGPUs anyway.
Though in the thin and light laptops, the 16CU part could operate at a lower frequency as that's more power efficient and still be faster. If RDNA 3.5 truly has a "fixed" V/F curve, it would be even better, though limited by memory bandwidth. I don't expect significant increases in iGPU performance until we get LPDDR6 (Strix Halo aside)
Subtlesnake
Regular
I was talking about clocks at a given TDP level, not max clocks. I think we're saying the exact same thing.
[AMDGPU] Add no return image_sample intrinsics and instructions by perlfu · Pull Request #97542 · llvm/llvm-project
An appropriately configured image resource descriptor can trigger image_sample instructions to store outputs directly to a linked memory location instead of returning to VGPRs. This is opaque to th...
github.com
So that must be what their compiler implementation for sampler feedback looks like. An image resource descriptor modifier in it's field which alters the behaviour of the image instructions ...
Not a whole lot, but some info on RDNA3.5:
Well Strix Halo is potentially chiplet-based, but yes, there's no word on this ever coming to discrete GPU products.
Frenetic Pony
Veteran
Yep
Also Strix Point doesn't scale well for (GPU) clockspeed because it gets bandwidth restricted almost immediately. Makes me believe that rumor it was going to have 16mb of cache for the GPU, but AMD made a quick turn around to a huge NPU after Microsoft pressured everyone into putting "AI" in instead.
At least Strix Halo has a shared systems level cache, 32mb apparently, so it'll scale much better if someone wants it in a NUC/Mac Studio kind of form factor.
Tangential but this is why I'm interested in how LPDDR6 CAMM2 does. 192 bit wide bus per module and approximate max of 2x MT/s vs DDR5/LPDDR5, potentially 3x bandwidth compared to most dual channel solutions today. 17.6GT/s, 192 bit bus = 422.4GB/s, 14.4GT/s = 345.6GB/s, both of which will drastically raise the ceiling on iGPU performance. A big laptop and handheld bottleneck reduced considerably at least momentarily
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