AMD RDNA3 Specifications Discussion Thread

[Erinyes]

But that's what we already have? The desktop APUs are literally the same chips as mobile APUs, only difference is packaging.

Yes that's again referring to the current mobile APUs which are also offered on desktop, along with the desktop specific parts like 7600X/7700X etc. What the rumour says is all mainstream mobile and desktop parts will be based off a single APU design and there won't be a desktop only design except for perhaps the high end.

That doesn't exactly make sense for gaming parts which would use dGPUs though as the IGP area which presumably would grow even more with the next gen would go to waste. And does desktop need an NPU as well as part of Microsoft's next push?

 

[Seanspeed]

But they're literally the same mobile APUs in desktop package

They're mobile+desktop APU's. They're both.

I mean, they explicitly support desktop memory. They aren't just mobile APU's.

EDIT: Ah I think I see what you're saying. There's already convergence here, yea.

 

[Kaotik]

https://twitter.com/x/status/1828795701712875562

Gonna go ahead and guess desktop launch is this year with this sudden burst of leaks from all over

(quoted from another thread)
I'm more interested on how to read the Strix Halo. April 16th 2025 would be one way to read the beginning, but the rest wouldn't make sense. But if it's not date, what would 16, 04 and 20 mean? 256 could be membus width since it matches, 32 probably IC MB and 8533 LPDDR5X-speed. Also what would the US Flag with park/mountain/river/something be? Doesn't match any codenames I can remember. And what would those numbers be, the obvious DDR5-6400 aside?

 

[Frenetic Pony]

(quoted from another thread)
I'm more interested on how to read the Strix Halo. April 16th 2025 would be one way to read the beginning, but the rest wouldn't make sense. But if it's not date, what would 16, 04 and 20 mean? 256 could be membus width since it matches, 32 probably IC MB and 8533 LPDDR5X-speed. Also what would the US Flag with park/mountain/river/something be? Doesn't match any codenames I can remember. And what would those numbers be, the obvious DDR5-6400 aside?

they're just "die code/bus width/l3 cache/gddr speed". Strix Halo does seem a cool part, I'm looking forward to CES, but I'm pretty sure this tweet is just RDNA4 specs.

 

[T2098]

(quoted from another thread)
I'm more interested on how to read the Strix Halo. April 16th 2025 would be one way to read the beginning, but the rest wouldn't make sense. But if it's not date, what would 16, 04 and 20 mean? 256 could be membus width since it matches, 32 probably IC MB and 8533 LPDDR5X-speed. Also what would the US Flag with park/mountain/river/something be? Doesn't match any codenames I can remember. And what would those numbers be, the obvious DDR5-6400 aside?

Zen5 'Fire Range' APU for high end mobile with DDR5-6400 maybe?

 

[Kaotik]

Zen5 'Fire Range' APU for high end mobile with DDR5-6400 maybe?

Fire Range is CPU rather than APU, it's Granite Ridge in mobile packaging (sure it had the basic 2CU GPU but...)

 

[Tkumpathenurple]

(quoted from another thread)
I'm more interested on how to read the Strix Halo. April 16th 2025 would be one way to read the beginning, but the rest wouldn't make sense. But if it's not date, what would 16, 04 and 20 mean? 256 could be membus width since it matches, 32 probably IC MB and 8533 LPDDR5X-speed. Also what would the US Flag with park/mountain/river/something be? Doesn't match any codenames I can remember. And what would those numbers be, the obvious DDR5-6400 aside?

I've not kept up with Zen 5 info all that well, but I seem to recall it was rumoured to use 16-core CCX's.

If that's the case, I'm guessing:
16 core full fat CCX
4 reduced cache 5c cores on the same die as the GPU
20CU's
256 bit bus
32GB's of 8533-LPDDR5X

Either that or it's all on the same die and we're looking at a 16 & 4 combination of full fat and reduced cache cores.

As someone who's itching for an architecturally updated PS4 portable, it looks fairly promising. Fingers crossed!

 

[no-X]

The second one seems to be Sonoma Valley, the tiny APU. 4 = 4 (Zen 5c) cores, 2 = 2 CUs (128 stream-processors), 64 = probably 64bit "single channel" bus, 6400 = supported memory speed.

Tkumpathenurpahl: Strix Halo should have 40 CUs (2560 stream-processors). So maybe 20 WGPs = 40 CUs. In this case, Sonoma Valley would have 2 WGPs = 4 CUs = 256 SPs(?)

 

[Kaotik]

16 core full fat CCX

It's 2x 8c CCX with halved cache (16 MB/CCD rather than 32 used in Granite Ridge CCX)

 

[Erinyes]

The second one seems to be Sonoma Valley, the tiny APU. 4 = 4 (Zen 5c) cores, 2 = 2 CUs (128 stream-processors), 64 = probably 64bit "single channel" bus, 6400 = supported memory speed.

Tkumpathenurpahl: Strix Halo should have 40 CUs (2560 stream-processors). So maybe 20 WGPs = 40 CUs. In this case, Sonoma Valley would have 2 WGPs = 4 CUs = 256 SPs(?)

Possible that Sonoma Valley has 4 CUs. It's a direct replacement for Mendocino which had 2 RDNA2 CUs which was a Q4'22 part and Sonoma Valley is a 2025 part so likely they'd want to up the graphics performance.

It's 2x 8c CCX with halved cache (16 MB/CCD rather than 32 used in Granite Ridge CCX)

Has this been confirmed anywhere? Unless I've missed it, all the leaks so far have said 32 MB/CCD.

 

[Kaotik]

Has this been confirmed anywhere? Unless I've missed it, all the leaks so far have said 32 MB/CCD.

You're right, I misread the image last night thinking it was halo in geekbench shot, but it was normal strix point for comparison

 

[Erinyes]

You're right, I misread the image last night thinking it was halo in geekbench shot, but it was normal strix point for comparison

Ahh okay. Yea so apparently it will have the same configuration as Granite Ridge i.e. 8 cores/32 MB L3, but curiously rumours are it will have a different CCD, i.e. different silicon, though still on 4nm. If it was 3nm then I would have understood but I don't understand the reason to tape out another CCD for a low volume part. The IOD with the RDNA 3.5 GPU is on 3nm, now that should give us a good idea of the kind of clocks the future Zen 6 mobile parts as well.

 

[no-X]

I don't understand the reason to tape out another CCD for a low volume part.

According to some rumors, Strix Halo won't have chiplets connected via package (like in desktop), but through an interposer. In this case, the chiplets would need to be equipped with a different interface. This solution may lower the power consumption and also work as a test vehicle for Zen 6 products. The interposer could also contain the 32MB SLC.

Instinct MI300A, which uses interposers, has such chiplets (just Zen 4-based). So AMD could theoretically use the new Zen 5 chiplets not only for Strix Halo, but also for the hypothetical successor of Instinct MI300A.

 

[Erinyes]

According to some rumors, Strix Halo won't have chiplets connected via package (like in desktop), but through an interposer. In this case, the chiplets would need to be equipped with a different interface. This solution may lower the power consumption and also work as a test vehicle for Zen 6 products. The interposer could also contain the 32MB SLC.

Instinct MI300A, which uses interposers, has such chiplets (just Zen 4-based). So AMD could theoretically use the new Zen 5 chiplets not only for Strix Halo, but also for the hypothetical successor of Instinct MI300A.

What you say may well be true for Strix Halo as I believe the Infinity Fabric is also being upgraded in some way but MI300A uses the exact same EPYC CCDs which Genoa uses, it is not a different physical design.

 

[DegustatoR]

AMD RDNA™ 3.5 Instruction Set Architecture (ISA) reference guide is now available

The AMD RDNA™ 3.5 ISA reference guide is now available! The ISA guide is useful for anyone interested in the lowest level operation of the RDNA 3.5 GPU architecture.

gpuopen.com