leoneazzurro
Regular
Hmm, to reach 2T you can do
1280(alu's) *2(fma)*781MHz,
1600(alu's)*2(fma)*625MHz,
Since rv770 already runs at 750MHz, the new shder count seems to be 16 SIMD's, downright tepid compared to rv670->rv770 transition.
And then there is of course the question of what are they doing with the ~350mm2 die area?
The sentence was "more than 2 Teraflops", we remember that also the HD4850 was exactly 1 Teraflop, so this time it could be that HD5850=2 Teraflops and HD5870>2 Teraflops too. Moreover, to have a big enough difference in performance between 5850 and 5870 to justify the price difference (as both will almost surely use GDDR5 this time) I think ATI has two options:
- to lower clock of 5850 substantially (20% or more)
- to make the 5850 a lower SIMD-count chip
Both options hints to an high amount of SIMD, as if the first one is true, then HD5850 needs an high number of SP to reach 2 teraflops, if the second is true, then it means that HD5870 will have a lot more SP than 5850 -> the maximum count of SP on the chip is high. I seriously doubt we'll see 900+MHz parts at launch, considering that tha 40nm process seems to have still some problems and that there could be thermal issues.
If we make a very rough calculation, a 2xRV770 chip in 40 nm will measure about 275 mm^2, let's throw in a 20% more area for DX11 compliance and improvements, and we have 330 mm^2. So if 350 mm^2 for Cypress is true, then it could fit well with a 1600 SP, 8 RBE chip (I hoped for evem more, though, as my first guess was 2000 SP, but who knows).