Are the current power draw and core voltages of Xenos and Xenon known? IIRC, the power consumption of an IC is roughly P = C*V^2*f + S [switch capacitance multiplied by supply voltage squared multiplied by frequency plus static consumption] and that the static consumption's share of the whole roughly double per process node.
Surely someone around here, with a bit more than my rudimentary understanding of EE, could make an educated guess as to how much they're likely to shave off by shrinking the two main ASICs.
Short version: It's hard to predict accurately without knowing almost everything they won't tell you during their design stages. It really depends on how they implement things.
There are lots of engineering decisions and experiments, and just knowing the voltages won't help all that much.
Maybe I'm just sidestepping some variables that should be best guesses or common knowledge, but my mind is a bit fragged right now.
Long version:
That's one equation... Actually, when considering the entire chip, there is a fractional term in front of the dynamic power, which indicates the fraction of transistors actively switching. So C is the total capacitance of all gates.
But things are very very...very complicated.
Dynamic Power
Code:
Pd= A*C*V^2*f
V = operating voltage
A= fraction of transistors that are active
C = capacitance of all gates
f = frequency of operation
There also exists some dependency between frequency, operating voltage, and the transistors' threshold voltage (to switch) so it's not that simple for power reduction via simple voltage change. The threshold voltage has to be reduced correspondingly with the operating voltage, and keeping that operational frequency is tricky.
Things are even trickier with the leakage current, which is a combination of sub-threshold and gate oxide leakages.
Static Power
Code:
S = V*(Isub + Iox)
Isub = K1 * W * (1-e^-(V/Vtheta)) * e^(- Vth / (n * Vtheta))
K1 & n are experimentally derived...
W = gate width
Vtheta = linearly temperature dependent voltage, ~25mV @ room temp.
Isub can increase to change the temperature and thus Vtheta increases accordingly though... yikes.
Vth = voltage threshold of the transistor,
For V to decrease, Vth must decrease too, otherwise the transistor will just be shut off. But decreasing Vth increases Isub exponentially...
So, decrease W...but then you get electron tunneling at that scale. Problems problems... It's not unlike decreasing the gate oxide thickness - see below for one of the solutions.
Things get tricky with the oxide leakage too:
Code:
Iox = K2 * W * (V/Tox)^2 * e^(- a * Tox / V)
K2 & a are experimentally derived (tough one to predict..)
Tox = physical gate oxide thickness
The problem with leakage current here is that as the process size decreases (including the gate oxide thickness), the Iox increases exponentially. The gate dimensions have to decrease so that the Vth decreases too.
In order to "increase" or "maintain" the physical Tox so that Iox and Vth are both reduced, they can use materials with larger dielectric constants to create an "effective silicon dioxide thickness".
In other words, the physical thickness is maintained or increased while the rest of the transistor gets smaller; Iox is reduced. But due to dielectric properties, the short channel effect is avoided as the electrons 'see' the effective silicon dioxide thickness, which is "thinner" - thus Vth is reduced.
Vth can also be decreased by increasing the doping concentrations, and that has its own issues. Things are extremely sensitive here.
There are numerous other solutions - take Intel's tri-gate for instance. It's a bit difficult to grasp with so many things to consider. :s
