Heh. Thanks for the exposition. :smile: Not too hard to follow, even for one such as myself (the last time I actively tried to learn about these things proper, Intel had just launched the Pentium).But things are very very...very complicated.
I guess I was thinking along the lines of: "Given what we know about the ICs current power profiles, node reductions in general (assuming that any redesign will be limited to fixing unexpected problems with static power), and the process they're using in particular; they're likely to reduce P by n to n'."
But I guess it's just too many variables to consider these days for such 'blanket estimations' to make much sense.