DegustatoR
Legend
TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips
www.anandtech.com
bigger is always better
It does feel a bit like 16nm vs 20nm… In many ways, A16 feels like N2P+backside and not much else, just like 16nm was mostly just FinFET. It’s quite disappointing N2P lost backside power delivery, that must be a very welcome surprise for Intel. I wonder how A16 compares to the *original* N2P with backside power delivery…
The density scaling is sufficiently bad that it seems to vindicate Intel’s High-NA strategy to some extent as necessary for density, although TSMC’s argument will be that doesn’t necessarily make the transistors/$ any better or significantly improve perf/power.
Still, I expect TSMC to be extremely competitive with Intel in practice for N2(non-P) vs 18A and beyond that, process nodes aren’t just about high level features and buzzwords, and TSMC has consistently delivered where it matters.
Taiwan Economic Daily reports that TSMC has seen its packaging supply wholly booked by AMD and NVIDIA. The CoWoS technology is being used for the development of NVIDIA's Hopper and the latest Blackwell GPUs while AMD is also leveraging it for its own MI300 accelerators.
The Taiwanese semiconductor giant plans to massively scale its production facilities in response to such huge demand. The company looks to achieve around 45,000 to 55,000 units of output by the end of this year, marking a vast YoY increase. This not only shows how big of a demand the industry is witnessing but also that TSMC has shown resilience and has gone to all extents to satisfy clientele demand.
I was wondering the same and was flipping back and forth between wafers and lots.What’s a single unit of CoWoS? One wafer’s worth of stacks?
In response to huge customer demand, TSMC is actively expanding its advanced packaging production capacity. Industry estimates indicate that TSMC's CoWoS monthly production capacity will reach 45,000 to 50,000 pieces by the end of this year, a multiple increase from 15,000 pieces in 2023. By the end of 2025, CoWoS's monthly CoWoS production capacity will reach a new peak of 50,000 pieces.
Literally from the article:Man, we're really going to go from N5(2020) to N3E to N2P to A16(2026) with a total of about 1.65x density improvement, and that only really being for logic.
Crazy times.
Well ok, fair enough if that's the case. It just makes the numbers beyond meaningless.Literally from the article:
*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
Doesn't it explain why the marketing numbers are low and getting lower?Well ok, fair enough if that's the case. It just makes the numbers beyond meaningless.
Not really. 50% of logic is a sizeable chunk in a formula and yet we're still looking at ".1x" density improvements. N5 to N3 is the last transition where there are noticeable improvements, and even that will be dissolved a bit because the difference between the most dense N5 version and the most dense N3 version will probably be smaller than between N5 and N3E from the spreadsheet.Doesn't it explain why the marketing numbers are low and getting lower?
But you are comparing that to previous numbers that didn't use this more "real world" formula.Not really. 50% of logic is a sizeable chunk in a formula and yet we're still looking at ".1x" density improvements. N5 to N3 is the last transition where there are noticeable improvements, and even that will be dissolved a bit because the difference between the most dense N5 version and the most dense N3 version will probably be smaller than between N5 and N3E from the spreadsheet.
Scaling is dead. There are no more "free transistors".
The "old formula" actually featured SRAM shrinkage though. Like 10 to 7nm was 0.83x fin pitch and 0.82x gate pitch for 47% higher logic density, while also HD SRAM cell size shrunk from 0.042 um^2 to 0.027. So a mix of 1.47x logic and 1.55x SRAM is in fact still 1.5x density across the chip. The issue with N3 is you're getting that same 1.5x logic, but only 1.05x SRAM, so balanced across the chip it's only 1.3x.But you are comparing that to previous numbers that didn't use this more "real world" formula.
TSMC listed N3 vs N5 at 1.7x but according to their "new" numbers N3E vs N5 is only 1.3x
N2's 1.15x = 1.3x
A16's 1.07x-1.1x = 1.14x-1.2x
So that would end up being >1.5x according to their old method.
Edit- They are in their incremental improvement phase since they need something new to offer every ~12-18months like they promised.
I don't think it did... most of the time TSMC was using logic density improvements in their marketing numbers.The "old formula" actually featured SRAM shrinkage though. Like 10 to 7nm was 0.83x fin pitch and 0.82x gate pitch for 47% higher logic density, while also HD SRAM cell size shrunk from 0.042 um^2 to 0.027. So a mix of 1.47x logic and 1.55x SRAM is in fact still 1.5x density across the chip. The issue with N3 is you're getting that same 1.5x logic, but only 1.05x SRAM, so balanced across the chip it's only 1.3x.
Though on the note of pitches, much of the density gains with 3nm are from DTCO-centric changes to standard cell layout, rather than reducing pitches. Which is also why SRAM isn't scaling, because it doesn't have extra fins to cut out.
Their marketing included both logic and SRAM, separately. Whether Anandtech included SRAM cell size that in their charts is a different matter.I don't think it did... most of the time TSMC was using logic density improvements in their marketing numbers.
That's how N3 vs N5 went from 1.7x to ~1.3x density.
Which is my point.
People are surprised to see the node's advertised density scaling going from the expected ~1.6x-1.8x down to 1.1x when it isn't apples to apples.
https://www.anandtech.com/show/1735...n3e-in-2024-n2-in-2026-major-changes-incoming
View attachment 11368
There were rumors(speculation?) that TSMC had already gotten one.https://wccftech.com/tsmc-yields-will-receive-high-na-chipmaking-machine-this-year-report/
TSMC Yields & Will Receive High NA Chipmaking Machine This Year – Report
interesting twist