My math earlier was off, so a billion transistor chip is doable within the confines of the 65nm process at a die size smaller than G80.
I'd expect that as long as SLI and Crossfire continue to have headaches, whichever GPU manufacturer can keep single-die solutions at a higher market segment will win out, if they don't lose money in the process.
Yes, but the wafer size and its effect on the area of silicon that can be produced by a fab has an impact on the costs of manufacturing a given die size.
My argument that larger die sizes than G80 and R600 are undesirable is a primarily economic one.
The cost per good die from a foundry goes up and variation starts to hurt binning out of that smaller pool of dies.
Lower binned chips can't be sold with good margins, even if the silicion itself is functional.
I tend to conveniently ignore these kind of issues.They are really not much of a concern for vendors who are using external fabs and standard cell design. So let me clarify: worst case electrical characteristic (which are always used to calculate the critical timing path of a chip) are really quite reliable, even in 65nm. Going forward, I don't expect major changes with this.
I suspect this is because fabs for one tend to add a certain margin of error exactly to make sure customers get what they expect.
I put too much emphasis on timings as opposed to the leakage variance.
On that note, G80 has parts that are not standard cell design, and R600 is an example where clock timings are likely good.
What has turned up is that AMD(ATI) with R600 has discovered what the CPU guys in every market but the extreme high end has known for years: that TDP and power draw is a first order limiting factor, regardless of circuit performance.
GPU price segmentation (and by extension the required binning) is odd.
For reasons I'm not sure I am fully aware of, the number of speed grades a given GPU die can be assigned is incredibly small compared to CPUs these days.
CPUs have over a half-dozen speed grades per chip stepping that become products.
GPUs like R600 will at the end of its life have only 3, and one is a cut down version, probably due to defects.
It can't go higher because of power draw, while it can't go too much lower with the cheaper to produce RV cores in the way.
I'm betting there is a fair amount of selection bias going on with GPU fabbing that neither Nvidia or AMD will disclose.
The CPU side is little better, they don't really give details on binning, but the wider selection of products provides more data points.
That may be more of a market segmentation thing and an engineering concern with regards to fixed TDP brackets for marketability.
It does help with crummy drive currents when you want that last GHz.
Intel does well on this account as well.
Most of those products don't seem need to push the envelope for performance or die size like top-flight GPUs, which in turn don't push the envelope on circuit performance like CPUs do.
That sort of begs the question why AMD's going the other route was so much slower...
I agree that as long as the design is highly repetitive internally, the debugging effort need only incrementally increase over a smaller design based on the same building blocks.Anyway, my main initial argument was that debugging chips with 1B transistors didn't have to be a major burden. We deviated quite a bit from that.
My concern is that the company might not make much money if the die size places the product at the wrong end of scaling trends.
The foundry isn't going to shield GPU designers from increased costs and fewer good dies per wafer start.
Once the inflection point where the costs in achieving a given level of performance versus the die area needed makes multi chip more cost effective, why not go multi-die?
