Sorry for being HT
I can understand that the rsx could read in the ppu cache (coherent memory)
I can understand that an spu can send data to the rsx.
I can't understant how the rsx could read spu ls (non coherent memory)( the other way around doesn't make sense ie spu reading rsx cache).
Anyway, the 35 GB/s cell/rsx seems useless if you don't aim at memory pools.
cell will send geometry data (not that much needed) and the cache of rsx will be full quiet quick if you don't aim for gddr3 ( sorry if dumb i try to understand).
For texturing it looks easier for for rsx to requet data in main ram, that lot of bandwith seems better suit for texturing, so it could be easily match buy a gpu with a wider bus to gddr, no???
(i'm trying hard to figure this clearly... i would not bet a penny on the result... lol)
/HT
HT again...
I can understand that it's usefull for xenon to send data to xenos, but what is the point for xenos to be able to read in the xenon L2 cache??
/HT
I can understand that the rsx could read in the ppu cache (coherent memory)
I can understand that an spu can send data to the rsx.
I can't understant how the rsx could read spu ls (non coherent memory)( the other way around doesn't make sense ie spu reading rsx cache).
Anyway, the 35 GB/s cell/rsx seems useless if you don't aim at memory pools.
cell will send geometry data (not that much needed) and the cache of rsx will be full quiet quick if you don't aim for gddr3 ( sorry if dumb i try to understand).
For texturing it looks easier for for rsx to requet data in main ram, that lot of bandwith seems better suit for texturing, so it could be easily match buy a gpu with a wider bus to gddr, no???
(i'm trying hard to figure this clearly... i would not bet a penny on the result... lol)
/HT
HT again...
I can understand that it's usefull for xenon to send data to xenos, but what is the point for xenos to be able to read in the xenon L2 cache??
/HT
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