Second Gen Cell info

[Mikage]

http://techon.nikkeibp.co.jp/article/NEWS/20050422/104072/
From Cool Chips forum in Japan

Code Name = DD2
Size:235mm2
Tape Out: end of 2004
Transitor:250 million
New feature:CPU core can do 2 Order at the same time.


First gen Cell:
Code Name = DD1
Size:221mm2
Transistor:234 million

Sorry, I am not good at English. But I wanted to write abut this info.

 

[blakjedi]

I thought the SPE in the current Cell could do 2 ops simulataneously.

 

[Mikage]

I thought the SPE in the current Cell could do 2 ops simulataneously.

Accroding to the article, DD1(Cell in ISSCC 2005) was that CPU core
(PPE) could do only 1 order simulaniously. And DD2 is made many
tuneup. Therefore chip size became a little bit bigger.

 

[one]

Cool Chips website and the program

I wonder about that 2-issue thing too. Maybe misinterpretation at Nikkei?

 

[Titanio]

Are we sure DD1 was the chip presented at the ISSCC, and not DD2? DD2 may have been the first Cell chip to be shown, even if one existed prior to it...(?)

edit - I wonder if there were ANY hints about possible PS3 implementations at that conference...even something very subtle. The first talk was by a SCEI guy, so I'd like to think it was possible

 

[one]

Are we sure DD1 was the chip presented at the ISSCC, and not DD2? DD2 may have been the first Cell chip to be shown, even if one existed prior to it...(?)

Apparently the tapeout of the DD2 was after the paper was submitted to the ISSCC referee (the DD1 tapeout was at the beginning of 2004), so unlikely.

 

[Titanio]

Are we sure DD1 was the chip presented at the ISSCC, and not DD2? DD2 may have been the first Cell chip to be shown, even if one existed prior to it...(?)

Apparently the tapeout of the DD2 was after the paper was submitted to the ISSCC referee (the DD1 tapeout was at the beginning of 2004), so unlikely.

Ah, i see, thanks.

Confusing, then..

 

[j^aws]

Just to clarify,

DD2 is a PPE that is 2-way SMT?

And DD1 isn't?

That's the only difference technically?

 

[one]

DD2 is a PPE that is 2-way SMT?
And DD1 isn't?
That's the only difference technically?

They report both DD1's "CPU core" and DD2's "CPU core" are SMT, but DD1's "CPU core" is single issue. It'll be clarified when Hofstee's paper is uploaded to the IBM Cell website.

 

[j^aws]

DD2 is a PPE that is 2-way SMT?
And DD1 isn't?
That's the only difference technically?

They report both DD1's "CPU core" and DD2's "CPU core" are SMT, but DD1's "CPU core" is single issue. It'll be clarified when Hofstee's paper is uploaded to the IBM Cell website.

Thanks, prolly explains why there was little detail revealed about the PPE at ISSCC...

 

[Mythos]

What ever happened to the cell presentation that was slated for 4/21-timeframe?

 

[V3]

I wouldn't call this second generation. But its a production revision IMO.

The DD1 is the prototype. DD2 is the production version. That's what I heard anyway.

 

[Andy]

I wouldn't call it second generation either, perhaps Version 2 (V2) or something.

 

[one]

That '2nd-generation' seems to correspond to '1st-generation' in the titles of the ISSCC Cell papers, but it's just their manner so 'revision' would be more understandable I guess (though it's said that the '2nd-generation' Cell is tuned towards less power consumption).

BTW, the article also briefly mentions the speech by Masakazu Suzuoki of SCE. Though it's said Kutaragi pushed 8 SPEs because he loves powers of 2, Suzuoki explained that they'd designed the Cell by analyzing the behavior of softwares actually running on things such as digital consumer electronics appliances, and the number of SPEs, for example, was determined by how application performance varies when the number of threads increases. The SPE architecture was defined toward optimization by compiler rathar than optimization in the instruction set, based on the experience in the Emotion Engine, for sometime a compiler fails to use a complicated instruction for a specific use.

 

[Fafalada]

Interesting pic.
http://ranobe.sakuratan.com/up/updata/up34102.jpg

This puts a PPE at almost exactly the same size as 2 SPEs (with their local mem included).
If Xenon CPU indeed has 2MB of L2, that will put it at ~90% of Cell 2nd gen die size (possibly larger if X-PPEs are larger by a noticeable amount) - or in other words, Well over 200mm2.

What was it that people were saying about XCPU being small(and cheap to produce) compared to Cell?

 

[Acert93]

If Xenon CPU indeed has 2MB of L2, that will put it at ~90% of Cell 2nd gen die size (possibly larger if X-PPEs are larger by a noticeable amount) - or in other words, Well over 200mm2.

Big "if". I thought they were going with 1MB? And as you know not all transistors are the same. Compare the cache heavy P4 with a video card...

 

[Fafalada]

Big "if". I thought they were going with 1MB?

2MB is just another recent rumour - but at least it's more credible then all the physics chip crap that's been flying around.

And as you know not all transistors are the same.

Actually I may have underestimated the size - 512KB block is just a tiny bit short of PPE size, so 2MB would occupy area of 7-8SPEs just for the cache. There's a chance 2MBL2 chip could be larger than the Cell...

 

[V3]

What was it that people were saying about XCPU being small(and cheap to produce) compared to Cell?

That's compare to the imaginary 4 Cells on a chip I think that's what people comparing it too.

What I want to know is how does the Wattage of Cell and Xenon CPU will compare. Or somekind of rough performance/wattage measurement.

 

[Fafalada]

That's compare to the imaginary 4 Cells on a chip Very Happy I think that's what people comparing it too.

Well recent debates about PhysxPPU usually included the assumption that MS can "easily afford" to add another large chip in there since their CPU will be relatively small and inexpensive compared to 8/1 Cell.

What I want to know is how does the Wattage of Cell and Xenon CPU will compare.

Yeah it's a good question - also would be nice knowing what PS3 Cell will really be like in the first place.

 

[passerby]

Hey wait a minute. Faf's talk is giving me the impression that many studios are not getting X360 close-to-final HW yet - not even one with the CPU(if we excused the GPU part).

Weird how things turn out. The 'late' Sony having already delivered a (admittedly hardly final)prototype CPU to studios.