Pricing Discussions around AMD VEGA *over-flow*

Discussion in 'Architecture and Products' started by pharma, Aug 17, 2017.

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  1. Grall

    Grall Invisible Member
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    Seems quite the increased complication if you have wires crossing the boundaries (which you'd pretty much certainly have inside a die I'd think...)
     
  2. CarstenS

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    Hence design for double exposure, i.e. minimizing critical structures crossing the threshold between the two exposure fields. Question is: Would such a design be possible in a high performance chip.

    Maybe someone with experience or insight into chip design can shed light on this aspect.
     
    #442 CarstenS, Sep 6, 2017
    Last edited: Sep 6, 2017
  3. 3dilettante

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    Going by the description of stitching across exposure regions for things like interposers and sensors, the feature size is measured in microns or significant fractions thereof. For large CMOS sensors, this is fine since for their purposes they have feature sizes greater than 10um and have the need for area and regular structure within their sub-units.

    It seems like the dimensions are favorable compared to the tens of microns in ubump pitch when mounting chips to an interposer, but once sufficient IO makes it to the interposer it looks like it would run out of room for the wires very fast if significant connectivity tried to cross the between regions. The +/- on alignment and sources of variation in the metal crossing the stitch are potentially 1-2 orders of magnitude beyond the usually cited 65nm process for interposers.

    http://www.ultratech.com/UT_Publications/Large Area Interposer/ECTC 2014 p541.pdf

    The process does add cost, perhaps with some factors like adding such fine levels of alignment concerns between exposed regions and the slowed rate in processing.
    One presentation also noted in this use case that stitched regions will have defect concerns to match their total area, and there are some failure modes unique to the laying down of metal across a region that has overlapping exposures.

    That might not be fully applicable to a GPU, but it seems like bypassing the exposure limit may give area that the GPU then cannot readily tie together.
     
  4. CarstenS

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    Yes, I see. Initially, I was not thinking along the lines of an interposer but maybe what can be described as a MCM-on-die. Like two halves of the complete chip with in this case maybe a number of Nvlinks between them. Those should lend themselves rather naturally to this kind of alignmend being intended for off-chip communication in the first place. Not going through the package but being on one die might even allow for faster speeds and better signal integrity despity multi-exposure. Of course, I was not so crazy as to assume you could allign regular intra-chip circuitry between two exposures.

    But I was just letting my mind wander, most certainly the cost would be prohibitive in the first place as well.
     
  5. 3dilettante

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    A passive silicon interposer is like an upper layer of metal without the complexity of an active layer or a lot of local connection complexity. Its behavior across a stitch boundary would be analogous to what would happen if metal layers in a GPU had to make a similar connection across a die boundary.

    Stitching like the interposer or sensors looks like it might be possible, but each layer of connections would have lower wire density due to needing physically massive feature sizes relative to what the GPU's internal regions are using.
    2.5D integration trades off area density in the mounted chips for PHY and bumps, but at least that lets the interposer's 65nm wire pitch carry many more signals horizontally between regions.
    I'd speculated about die stitching in this manner before, but if those density numbers are applicable it may explain why it hasn't been pushed. Getting enough thick metal layers to get comparable bandwidth or creating an on-die high-speed interface that acts like an off-die one, appear counterproductive.

    Some other form of region-crossing would have to be implemented that differs from this method.
    Non-connected methods like capacitive coupling or some kind of RF link have coarse area requirements, which in this case could become prohibitive as they would need to fit along a die edge and have the Z-height of the chip as their pad space.

    I've thought about some kind of directed self-assembly or other method of growing connections, but that would be extra manufacturing after all the rest of the GPU silicon was done and that kind of tech is still discussed in the future tense.
     
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  6. ToTTenTranz

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  7. Rodéric

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    But current Vega are as silent as vacuum cleaners...
     
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  8. ToTTenTranz

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  9. Rodéric

    Rodéric a.k.a. Ingenu
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  10. entity279

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    You are correct about 3dB (not that i'm a sound engineer). However , I don't think measurements from site to site are comparable
     
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  11. ToTTenTranz

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    Sound perception depends in pressure (measured in dBA) and pitch (frequency of the sound) . The pitch at which the noise is made is also pretty important for the perception of sound (our ears give huge boosts in sound perception between 2KHz and 5KHz because human speech stands between those).
    In Power Saving mode the V56 runs at 1750rpm and the V64 at 1950rpm. These fans aren't running very fast so their noise has a low pitch.
    So while soundmeters might tell the impression that the cards are loud, anecdotal listening tests will say otherwise.
    I know my card is pretty much inauble in power saving.
     
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  12. CarstenS

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  13. Rodéric

    Rodéric a.k.a. Ingenu
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    Yep found it too after posting, so not that bad still about 33% worse though...
    Will wait for custom parts to arrive, might be better.
     
  14. entity279

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    My point still stands - each review environment has pottentially a different noise floor. So dB measurements are not comparable from one review to another
     
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  15. Rodéric

    Rodéric a.k.a. Ingenu
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  16. CarstenS

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    Sure, but even the anechoic-ness can vary quite a lot. World record still is Microsofts AC with -20,6 dB(a):
    https://venturebeat.com/2015/10/01/...amber-officially-the-quietest-place-on-earth/

    In our (semi-)anechoic room, we can measure down to 13,4 dB(A) IIRC and that's a quietness-level, where the loudest thing you perceive is the blood flowing through your ears already. Makes me crazy if I'm in there for too long, have to take a break every 15 minutes or so.

    Many people just measure in their office rooms, usually after hours and with a noise floor of about 25-30 dB(A). Also, the distance between sound source and microphone often varies a lot. Some do ISO-conformant 100 cm, some go as close as 5 -10 cm. It's also a difference whether your measure perpendicular to the fan axis or from the top, while the card is installed in a usual tower case.
     
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  17. entity279

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    Sounds exciting to me though, I just can't believe too much quietness can ever be a bad thing
     
  18. Alexko

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    A friend of mine reported the same thing, apparently hearing your own heartbeat can be somewhat disturbing.
     
  19. entity279

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    oh wrt to hearing your own heartbeat, there should be a filter in the brain (or hearing system?) that should take out just that. Quite possibly this is only an attenuation , and when the noise floor is low we can still hear it.

    A doctor that dealt with these told me that there's even a condition where this filter doesn't work, unfortunately . It's apparently maddening to constantly hear the heartbeat at full force.
     
  20. Grall

    Grall Invisible Member
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    When I work strenuously physically it often happens that the pipes in my head open up and my own breathing becomes incredibly loud in my ears. This is quite irritating, I must say.
     
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