AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

Did anyone else sit up and take notice at Lisa Su's mention of improved Vega cores for the Ryzen 4000 during CES?

"If you notice, the frequencies are super high – AMD said that this enhanced version of Vega, architected for 7nm, actually responded really well in terms of frequency and power, and so they were able to boost the clocks up a lot. So despite the drop from 11 CUs in the silicon design down to 8 CUs, the 1750 MHz frequency really piles on the performance. AMD is promoting +28% GPU performance in 3D Mark Time Spy against Intel’s Core i7-1065G7[.]"

I wonder if this rearchitecting is a peek into what can be expected from Arcturus? Seems Vega is going strong for now.

 

Isn't that an up-to frequency? Same ballpark as Radeon VII, which is 7nm Vega as well.

 

Drat, forgot that the current Vega APU's are on 14 nm.

 

The bigger question is what are the other tweaks made to the architecture. They quoted "nearly 60% faster" cores, but clocks explain only 25 of those 60% so there's 35 from something else.

 

Is there a footnote coming with „nearly 60% faster“? Could be a combination of higher clocks, lower power and vastly (45%) faster memory.

 

Oh, right, they did mention LPDDR4X

 

There would be little point doing big ass chip like that into datacenters if it didn't.

Agreed, so I answered here instead, mods could add Arcturus to the title​

 

FYI, Dr. Bradley McCredie, who recently joined AMD as a corporate vice-president, made a presentation at the 2020 Oil and Gas HPC Conference at Rice University and disclosed that future Radeon GPUs will support cache-coherent shared memory.

https://wccftech.com/amd-next-gen-e...u-accelerator-power-el-capitan-supercomputer/
https://www.tomshardware.com/news/amd-infinity-fabric-cpu-to-gpu

 

That was also said in the El Capitan Announcement slides.

 

GCN for compute becomes CDNA, Arcturus apparently first CDNA chip, CDNA has "less graphics bits" which fits Arcturus' "it has no 3d engine"
https://www.anandtech.com/show/1559...a-dedicated-gpu-architecture-for-data-centers among others

 

https://www.anandtech.com/show/1559...a-dedicated-gpu-architecture-for-data-centers

 

Are you afraid that this could backfire ? Like, making 2 différents arch in // will stretch RTG ressources too much ?

 

Or actually fit better with the limited R&D resources, preventing the development of complicated all-in-one architecture.

 

CDNA is essentially a rebranded GCN for now. I fully expect it to switch to the same RDNA base architecture down the road.

 

These days it might be harder to distinguish what is "new architecture", but RDNA is still very much GCN too and it's referred as "GCN 1.5" (and 1.5.1 for Navi+DLops) at least in certain contextes

 

RDNA is not GCN, it has a completely different execution pipeline. This pipeline isn't any worse for compute than GCN's so I expect AMD to just switch to RDNA base architecture in some "CDNA2" product, maybe with some HPC specific tweaks as well (fast FP64, cut down ROPs and such).

 

Actually it is worse for compute. Changes implemented in RDNA required a lot of transistors, which have no impact on pure compute performace. Vega 20 offers 1,05 TFLOPS per 1B transistors, Navi 10 offers 0,95 TFLOPS per 1B transistors. Despite Navi's higher clocks and despite Vega's support for wider range of precisions, which cost transistors.

 

Like I said, it's harder to distinguish what's "new architecture" and what not, as so much DNA of the "old architecture" gets always carried over. It still doesn't change the fact that in some contextes RDNA is still referred as GCN.
Like no-X said, it is worse for compute in terms of transistor budget. CDNA looks to be GCN1.4.x (since it's gfx9xx (908 IIRC)), biggest changes to 1.4.1 (Vega 20) should be removing some graphics related blocks

 

https://www.notebookcheck.net/This-...-CU-despite-still-being-on-Vega.449849.0.html

It was explain by Robery Hallock on twitter

 

There is more to GPGPU performance than simply the number of TFLOPS on the chip. Otherwise terascale would have been the greatest compute architecture known rather than generally incapable of it. Or take a look at nvidia's diverged designs: their compute focused ones have more SRAM and less TFLOPS per area than gaming. Things like larger and higher bandwidth caches or needing fewer waves to occupy a wavefront bring a larger benefit the more sophisticated a shader is and the less coherent its memory access. And rasterisation has very simple shaders and highly coherent access in the grand scheme of massively parallel algorithms