Predict: The Next Generation Console Tech

[MarkoIt]

256 bit bus @ 6Gbps / pin, - hot and expensive, IMHO.

Cheers

I think it too, and the chips are "simply" 8x4 Gbit chips. Offcourse, IMHO.

I'm basing my speculation on the idea that Sony is spending less money on the R&D of next-gen hardware than MS. Sveetvar said that Durango's SoC was a higher priority project for AMD: i think it's because it's a more complex design. And the "secret sauce" rumor confirms that.

 

[Bagel seed]

I suspect it was a higher priority because AMD was doing most of the work for them there in helping them figure out the SoC and custom APU. Whereas Sony's taking the advanced chip packaging route and just gathering the parts they need from suppliers.

 

[ShadowRunner]

Is 192GBs achievable with stacked DDR3/4 on a 512-bit interface?

 

[Love_In_Rio]

Is 192GBs achievable with stacked DDR3/4 on a 512-bit interface?

I think you need a 1024-bit one for that ( DDR4 ).

 

[anexanhume]

I think you need a 1024-bit one for that ( DDR4 ).

Yup. Figure 6 GHz GDDR5 on a 256 or 384 bus is needed for north of 200 GB/s numbers. If you third the transfer rate, you have to triple the bus. That means 768 or bigger.

 

[Hecatoncheires]

Hey guys,

I have a few questions concerning the rumour of an APU and GPU combination concerning the new PlayStation, if that is agreeable. Maybe someone can bring a little light into my darkness.

I stumbled upon this slide from the Fusion Developer Summit which took place in June 2012. The slide deals with GPGPU algorithms in video games. There are a couple of details that are probably somewhat interesting when speculating about a next generation gaming console.

As far as I understand, AMD argues that today GPGPU algorithms are used for visual effects only, for example physics computations of fluids or particles. That is because developers are facing an insurmountable bottleneck on systems that use homogeneous processor architectures. AMD calls it the copy overhead. This copy overhead originates from the copy work between the CPU and the GPU that can easily take longer than the processing itself. Due to this problem game developers only use GPGPU algorithms for visual effects that don't need to be sent back to the CPU. AMD's solution for this bottleneck is a unified adress space for CPU and GPU and other features that have been announced for the upcoming 2013 APUs Kabini (and Kaveri).

But these features alone are only good for eliminating the copy overhead. Developers still have to deal with another bottleneck, namely the saturated GPU. This problem is critical for GPGPU in video games since the GPU has to deal with both, game code and GPGPU algorithms at once. I'm not sure whether this bottleneck only exists for thick APIs like DirectX or if it also limits an APU that is coded directly to the metal. Anyway, AMD claims that a saturated GPU makes it hard for developers to write efficient GPGPU code. To eliminate this bottleneck AMD mentions two solutions: Either you can wait for a 2014 HSA feature that is called Graphics Pre-Emption, or you can just use an APU for the GPGPU algorithms and a dedicated GPU for graphics rendering. The latter is what AMD recommends explicitly for video gaming and they even bring up the similarities to the PlayStation 3, which renownedly uses SIMD co-processors for all kinds of tasks.


I would like to know what you guys think about these slides.


What if AMD was building an 28nm APU for Sony that is focused solely on GPGPU, for example four big Steamroller cores with very fast threads in conjunction with a couple of MIMD engines? Combine it with a dedicated GPU and a high bandwidth memory solution and you have a pretty decent next gen console.

I would also like to know if an APU + GPU + RAM system in package is possible with 2.5D stacking, which was forecasted by Yole Development for the Sony PlayStation 4, for IBM Power8 and Intel Haswell.

And since Microsoft is rumoured to have a heavily customized chip with a "special sauce", could that mean they paid AMD to integrate the 2014 feature Graphics Pre-Emption in the XBox processor, so they can go with one single ultra-low latency chip instead of a FLOP-heavy system in package?

 

[Brad Grenz]

I think you need a 1024-bit one for that ( DDR4 ).

That's what I'm thinking it will actually be. Committing to GDDR5 long term at this point seems risky, and considering Vita, Sony is eager to user 2.5D and 3D stacking techniques. I could see as much as 8GB on a WideIO DDR4 setup. It solves their bandwidth requirements and their capacity deficit.

I'm also guessing MS will use DDR3/4 on a conventional 256bit bus, because if they were going for stacked memory too, why are they wasting all that die space on a big bank of embedded memory?

 

[anexanhume]

That's what I'm thinking it will actually be. Committing to GDDR5 long term at this point seems risky, and considering Vita, Sony is eager to user 2.5D and 3D stacking techniques. I could see as much as 8GB on a WideIO DDR4 setup. It solves their bandwidth requirements and their capacity deficit.

I'm also guessing MS will use DDR3/4 on a conventional 256bit bus, because if they were going for stacked memory too, why are they wasting all that die space on a big bank of embedded memory?

It was MS that fell in love with the APU approach arguably with the slim. If they are going to do an APU but then do a conventional bus, stacking must be out because of the schedule impact, heat concerns, or cost. I don't see them needing to be less risk averse than Sony, which would lead me to conclude a larger TDP for their APU.

 

[upnorthsox]

Is 192GBs achievable with stacked DDR3/4 on a 512-bit interface?

Yes. Someone did the arithmetic a little while ago, Gipsel I think, and the BW turned out to be right there at 190GBs for moderately clocked ddr.

 

[upnorthsox]

I think it too, and the chips are "simply" 8x4 Gbit chips. Offcourse, IMHO.

I'm basing my speculation on the idea that Sony is spending less money on the R&D of next-gen hardware than MS. Sveetvar said that Durango's SoC was a higher priority project for AMD: i think it's because it's a more complex design. And the "secret sauce" rumor confirms that.

And what does any of this have to do with gddr5 being hot and expensive? I'd say baseless.

 

[upnorthsox]

256 bit bus @ 6Gbps / pin, - hot and expensive, IMHO.

Cheers

Right, that's why everyone has dropped it for ddr3..........

 

[upnorthsox]

A Ps4 with APU 4 cores cpu + 1024 alus/Simd/Shader cores at 900MHz and 4GB GDDR5? That could be very interesting indeed.

Fyi

18CU's = 1152 ALU's.

 

[Brad Grenz]

It was MS that fell in love with the APU approach arguably with the slim. If they are going to do an APU but then do a conventional bus, stacking must be out because of the schedule impact, heat concerns, or cost. I don't see them needing to be less risk averse than Sony, which would lead me to conclude a larger TDP for their APU.

AMD loves APUs. MS just took the obvious route to cost reduction for the 360 (years after the PS2 was shrunk to a single CPU/GPU I might add).

Maybe they went with a conventional memory design because it would be suicide to compound the rumored yield issues they are already having with a cutting edge interposer architecture.

 

[N2O]

I think it too, and the chips are "simply" 8x4 Gbit chips. Offcourse, IMHO.

I'm basing my speculation on the idea that Sony is spending less money on the R&D of next-gen hardware than MS. Sveetvar said that Durango's SoC was a higher priority project for AMD: i think it's because it's a more complex design. And the "secret sauce" rumor confirms that.

About "higher priority project for AMD",i saw a may not important but pretty interesting respond by #1 AMD china guy,from yesterday
"倒是接微软的这个活让大家都能活的滋润些，所有费用都是微软出，包括工资。。。感觉是个微软的外包了。。。农企也觉得这样很好，打算成立个新的BU了。。。

一句话，农企彻底变打工卖苦力的了"

He said "Microsoft pay for them everything,even including wages,he feel like he is(or AMD Durango team is) Microsoft's outsourcing team now,but AMD think that's good,and and intends to set up a new BU(what is BU?)

In short,AMD become a company working for someone"

 

[anexanhume]

AMD loves APUs. MS just took the obvious route to cost reduction for the 360 (years after the PS2 was shrunk to a single CPU/GPU I might add).

Maybe they went with a conventional memory design because it would be suicide to compound the rumored yield issues they are already having with a cutting edge interposer architecture.

Which goes back to what I was saying. Yield issues usually means complex design or big die. Components are APU are mostly tested AMD designs. That leaves big die. Big die means high TDP.

 

[jaosobno]

AMD think that's good,and and intends to set up a new BU(what is BU?)

Business Unit?

 

[McHuj]

BU = business unit.


Back on PS4, I think 4GB of GDDR5 is doable. It would have to be 8 4Gb chips.

I think the heat/power consumption is tolerable, my guess it would be around 30-40W. I'm assuming the 4Gb chips would be on a smaller node than what is out there now, so power consumption should go down.

My guess that the APU consisting of 2 Piledriver/Steamroller modules + 1152 shaders and the memory would consume around 150W. Overall system power would probably be very similar to launch PS3. You're basically looking at a down clocked Radeon 7870 card with double the density GDDR chips and two CPU modules in the GPU.

I think the bigger hurdle to the use of 4GB GDDR5 is volume and cost. I can easily see the memory being much more expensive then the APU.

 

[Prophecy2k]

Which goes back to what I was saying. Yield issues usually means complex design or big die. Components are APU are mostly tested AMD designs. That leaves big die. Big die means high TDP.

Or that MS' customisations to the existing AMD designs mean that it's a much more complex APU than AMD has produced thus far.

 

[anexanhume]

Or that MS' customisations to the existing AMD designs mean that it's a much more complex APU than AMD has produced thus far.

Which to me is just as exciting as a huge APU with an off the shelf 2TF+ GPU.

 

[pjbliverpool]

Yes. Someone did the arithmetic a little while ago, Gipsel I think, and the BW turned out to be right there at 190GBs for moderately clocked ddr.

DDR3/4 1600 (a fairly moderate speed) would provide 102.4 GB/s on a 512bit bus if I'm not mistaken. So it would need a 1024bit bus to get near 192 GB/s but even then it would amount to 204.8 GB/s.

To get 192 GB/s you would need 1500Mhz memory on a 1024 bit bus. That sounds like a strange combination to me. Obviously 6Ghz GDDR5 on a 256 bit bus is a well known setup already being what the GeForce 670/680 use.