According to AMD, a single Jaguar core is 3.1 mm². Let's say we're looking at a quadcore implementation, we're looking at 12.4 mm² for the cores and 2 MB of cache on TSMC's 28 nm process should be roughly 6 mm². Those numbers are a little optimistic probably, so let's say that a Jaguar quadcore implementation including cache is around 25 mm². An 8-core implementation would be around 50 mm² according to those numbers actually.
BTW, that cache size calculation is done assuming a cache density of 3 Mbit/mm², which pretty much is the maximum cache size possible on TSMC/s 28 nm process and probably a little optimistic in this case. 2 Mbit/mm² is probably more realistic, which results in an L2 cache size of 8 mm². 25 mm² total for a quadcore implementation isn't so unrealistic in other words.
EDIT: My pie in the sky SoC would be this:
-24 CU (1536 SPs) 24 ROPs, 96/48 Texels filtered/clock (int/fp16) and a double rasterizer like on Tahiti. Size should be roughly 225 mm².
-8 Jaguar cores with 4 MB L2 cache total. Size roughly 50 mm².
-64 MB eDRAM L3 cache. Size roughly 45 mm².
-256-bit memory bus and other bits and pieces. Size ~65 mm²
Total Die size is 385 mm². Clocks should be 1.6 to 2 GHz for the CPU cores and 750 MHz for the GPU. TDP around 150 Watts.
8 GB of DDR4 memory at 3200 MHz for a 102 GB/s bandwidth, or 8 GB of GDDR5 memory at 6000 MT/s for 192 GB/s.
Well, as I'm saying, it's a bit pie in the sky, but one can hope .
A pitcairn is ~ 212mm² with 20 CU including the 256-bit memory bus size?
I dont understand why a 24CU variation would be significantly bigger?