I wish that would be true, power 8 or a custom power 7+ on IBM 32nm process.
Actually the overall design for the 360 proved to be quiet successful, the only draw back was the Edram which remained unchanged at 10MB when MSFT decided to move to 720p /HD resolution as the target resolution for the system.
It could be achievable to deliver the jump in performances people wants while actually possibly lowering a tad the silicon budget vs the 360.
I'm not sure about how big would be a quad core power 7+ with a sane amount of L3 (not 10MB per core) vs Xenon. Looking at a power 7+ die shot as this
one they look indeed pretty tiny.
Then you have the massive L3 interconnect, the SMP links, memory controllers, accelerators, etc.
I would think that a "ROPless" HD 7850 (16 CUs native) with let say three memory channel /192 bit bus to DDR3 would end in the same ball park as Xenon. Pitcairn is 202 mm^2 and CUs seems to take a lot of that space (Anandtech among others has die shots available
here ).
In a "native" HD 7850" (as I describe it), that is 20% less space allocated to the CUs, no ROPs, 25% less space taken by the memory controllers, I would not be too surprised if the chip ends up at least 20 % tinier than pitcairn, that would be a max estimate of 200 mm^2 minus 40mm^2 so 160 mm^2.
That left the smart edram, using IBM 32nm process, too I would not expect 64MB to be that big.